Memory device, memory controller and memory system

ABSTRACT

Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof. A memory device that is operated in response to a command from a memory controller has a plurality of banks that respectively have memory cores including memory cell arrays and decoders and are selected by bank addresses; and a control circuit, which, in response to a background refresh command, causes the memory cores within refresh target banks set by the memory controller to successively execute refresh operation a number of times corresponding to refresh burst length that is set by the memory controller, and, in response to a normal operation command, further causes the memory cores within banks other than the refresh target banks and selected by the bank addresses to execute normal memory operation corresponding to the normal operation command, during the refresh operation executed by the memory cores within the refresh target banks.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromthe prior Japanese Patent Application No. 2006-345415, filed on Dec. 22,2006, Japanese Patent Application No. 2007-10763 filed on Jan. 19, 2007,and Japanese Patent Application No. 2007-27827, filed on Feb. 7, 2007,the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Technical Field

The present invention relates to a memory device for recordingtwo-dimensionally arrayed data including digital image data, a memorycontroller of the memory device, and a memory system. Particularly, thepresent invention relates to a memory device, memory controller andmemory system for increasing an effective bandwidth indicating thenumber of data items that can be processed per unit time.

2. Prior Art

The market size of the memory devices for recording two-dimensionallyarrayed data, like digital image data, has been gradually increasingalong with the popularization of video distribution through digitalbroadcasting or the Internet. Digital image data is a group of dataobtained by constituting gradation information of pixels using aplurality of bits (e.g., 256 gradation levels of 8 bits). For example,one frame of image data for high-definition broadcasting is constitutedby 1920×1040 pixels. Each frame of this image data is arranged in anaddress space within image memory in accordance with a predeterminedmapping method.

Such memory mapping is defined so that the most efficient access can bemade, on the basis of the configuration and operation of synchronousDRAM (SDRAM) that is presently popular. For example, SDRAM has aplurality of banks, and each bank has a plurality of word lines and bitlines, a plurality of memory cells that are at the intersections of theword lines and bit lines, and sense amplifiers corresponding to the bitlines. The plurality of banks can independently execute activeoperation. The active operation performed in the SDRAM is a series ofoperations for selecting a word line and activating the correspondingsense amplifier on the basis of a row address. Further, read operationperformed in the SDRAM is a series of operations for outputting abit-line potential as read data to an input/output terminal on the basisof a column address, the bit-line potential being amplified by the senseamplifier, while write operation is a series of operations for inputtingselected write data, which is inputted from the input/output memory, toa bit line that is selected based on the column address.

An address space within a memory of the SDRAM is constituted by aplurality of page areas each of which can be selected by a bank addressand a row address, and each of the page areas has a group of bits or agroup of bytes that can be selected by a column address. The group ofbytes (or the group of bits) that are selected by the column address areinputted/outputted via a plurality of input/output terminals.

According to a generally known mapping method, a pixel of digital imagedata is associated with each byte (or bits) of the group of bytes (orthe group of bits) that can be selected by the column address within apage area. Moreover, according to this mapping method, each of the banksof the SDRAM can independently execute the active operation and the reador write operation, thus the plurality of page areas associated with anarrangement of pixels of the digital image data are arranged so thatpage areas that are vertically and horizontally adjacent to each otheron the image correspond to different bank addresses respectively. Forexample, if the SDRAM is constituted by four banks, the page areascorresponding to bank addresses BA=0, 1 are alternately arranged in theodd-numbered rows, while the page areas corresponding to bank addressesBA=2, 3 are alternately arranged in the even-numbered rows. By arrangingthe page areas in this manner, when reading or writing one frame ofimage data, different banks can execute the active operation and theread or write operation alternately and temporally overlapped, and abandwidth, which is the number of processable pixels per a unit time,can be increased remarkably.

Patent Documents 1 and 2 describe that the access efficiency is improvedby allowing simultaneous access to a plurality of rows in asemiconductor memory for storing image data.

Furthermore, Patent Document 3 describes a memory device that isprovided with a sub-array selection circuit for performing control toactivate, simultaneously, a sub-array allocated to an input row addressand a sub-array allocated to a row address right above the input rowaddress, in order to solve the increased reading time and powerconsumption since the data in every other row need to be read when usingthe DRAM in image expansion processing.

However, Patent Document 3 is designed to enhance the efficiency ofhorizontal accesses that are made continuously in a row direction of theimage, and thus does not describe the rectangular access.

Moreover, Patent Document 4 describes a data processing system in whicha bus controller issues an address active command, in response to anaccess instruction sent from a data processing section, to a storagearea different from a storage area accessed in a burst mode, and therebysetting of an access address is made possible. Specifically, while thememory controller activates and accesses one bank, an active command isissued to other bank to perform active operation before hand on thisbank, whereby acceleration of read/write operation can be realized.

Also, Patent Document 5 discloses an image processing device having: animage memory; and a control unit for continuously generating a columnaddress while accessing an arbitrary bank, to continuously access anarbitrary address within the same page, and row-activating a bank to besubsequently accessed in advance and thereby immediately accessing thebank to be newly accessed even if accessed bank is switched to anotherbank. Specifically, there is described that the memory controller has anaddress order prediction circuit to predict a bank to be subsequentlyaccessed and issue an active command to the memory.

Patent Literature 6 describes a memory system, wherein a volatile memoryis provided in a plurality of banks, a refresh target bank is specifiedby an auto-refresh command, and, during a refresh operation performed bythe refresh target bank, the banks other than the refresh target bankexecute a normal memory operation in response to a normal memoryoperation command. However, Patent Literature 6 does not describe that aplurality of refresh counts are set beforehand to perform refreshcontrol.

Patent Literature 7 describes a memory device in which a dual port DRAMis divided into a plurality of banks, and a data read transfer cycle isperformed on one bank in synchronization with a refresh cycle performedon other banks.

Patent Literature 8 describes that the memory controller executes accesscontrol on the SDRAM with two banks to read and write-data, and performsrefresh operation by issuing an active command and a pre-charge commandto a bank different from the accessed bank.

Patent Literature 9 describes that in the case in which access andrefresh are generated simultaneously in a DRAM with two blocks, or inthe case in which access has been already generated in one block, anarbiter causes the other block to execute refresh operation, and causesthe former block to execute access operation.

[Patent Literature 1] Japanese Unexamined Patent Application PublicationNo. 2001-312885

[Patent Literature 2] Japanese Unexamined Patent Application PublicationNo. H08-180675

[Patent Literature 3] Japanese Unexamined Patent Application PublicationNo. H09-231745

[Patent Literature 4] Japanese Unexamined Patent Application PublicationNo. 2002-132577

[Patent Literature 5] Japanese Unexamined Patent Application PublicationNo. H10-105367

[Patent Literature 6] U.S. Patent Application Publication No.US2005/0265104A1

[Patent Literature 7] Japanese Unexamined Patent Application PublicationNo. H08-115594

[Patent Literature 8] Japanese Unexamined Patent Application PublicationNo. H09-129881

[Patent Literature 9] Japanese Unexamined Patent Application PublicationNo. H10-11348

The occurrence of a decrease of the effective bandwidth is not limitedin the rectangular access. In a generally-used synchronous DRAM (SDRAM),in response to an auto-refresh command issued from the memorycontroller, refresh operation is performed in all banks in parallel onthe basis of the refresh addresses of the refresh address counters thatare commonly provided in the memory. For this reason, once the refreshoperation is started, neither horizontal access nor rectangular accesscan be executed, and the access operation needs to be kept in standbyuntil the refresh operation is ended. As a result, the effectivebandwidth decreases.

An object of the present invention, therefore, is to provide a memorydevice in which the decrease of the effective bandwidth caused by therefresh operation of the memory device has been solved, a memorycontroller of the memory device, and a memory system thereof.

DISCLOSURE OF THE INVENTION

In order to achieve the above object, according to a first aspect of thepresent invention, there is provided a memory device having: a pluralityof banks that respectively have memory cores including memory cellarrays and are selected by bank addresses; and a control circuit, which,in response to a background refresh command and refresh burst lengthinformation, causes the memory cores within refresh target banks tosuccessively execute refresh operation a number of times correspondingto the refresh burst length information.

In order to achieve the above object, according to a second aspect ofthe present invention, there is provided a memory device that operatesin response to a command sent from a memory controller, the memorydevice having: a plurality of banks that respectively have memory coresincluding memory cell arrays and are selected by bank addresses; and acontrol circuit, which, in response to a background refresh command,causes the memory cores within refresh target banks set by the memorycontroller to successively execute refresh operation a number of timescorresponding to refresh burst length that is set by the memorycontroller, and, in response to a normal operation command, furthercauses the memory cores within banks other than the refresh target banksand selected by the bank addresses to execute normal memory operationcorresponding to the normal operation command, during the refreshoperation executed by the memory cores within the refresh target banks.

In the second aspect of the present invention, according to a firstpreferred embodiment, the memory device further has: a refresh addresscounter that counts refresh target addresses within each of theplurality of banks or within each of a plurality of groups of theplurality of banks. Also, the control circuit has: a background refreshcontroller that outputs refresh control signals to the set refreshtarget banks in response to the background refresh command; a refreshburst length register in which the refresh burst length is set; and acore controller that is provided in each of the plurality of banks, and,in response to the background refresh control signals, causes the memorycores to execute refresh operation on the addresses of the refreshaddress counter a number of times corresponding to the refresh burstlength set in the refresh burst length register.

In the second aspect of the present invention, according to a secondpreferred embodiment, a refresh block count that indicates the number ofmemory blocks activated simultaneously in a single refresh cycle is setby the memory controller, and the control circuit causes the refreshtarget banks to execute the refresh operation a number of timescorresponding to the set refresh burst length, in response to thebackground refresh command, the refresh operation being performed forsimultaneously activating the blocks for the number of the refresh blockcount. The refresh block count is set by a mode register in advance.Alternatively, the refresh block count is inputted and set along withthe background refresh command.

In the second aspect of the present invention, according to a thirdpreferred embodiment, the refresh burst length and the refresh blockcount are inputted simultaneously with the background refresh command.Alternatively, the refresh burst length and the refresh block count areinputted simultaneously with a mode register setting command. In thefirst case, the refresh burst length register is provided in each of thebanks, and the inputted refresh burst length is set in the refresh burstlength register with in the refresh target banks. Further, a refreshblock count register is provided, and the refresh block count that isinputted is set in the refresh block count register. In the latter case,the refresh burst length register is provided within the mode register,and the inputted refresh burst length is set in the mode register.Similarly, the refresh block count register is provided within the moderegister, and the refresh block count that is inputted is set in themode register.

In the second aspect of the present invention, according to the thirdpreferred embodiment, during the refresh operation executed a number oftimes corresponding to the refresh burst length, the core controllercauses, in response to a newly inputted background refresh command, thememory cores within the refresh target banks to successively execute therefresh operation a number of times that is obtained by adding therefresh burst length to the remaining number of times of the refreshoperation.

Alternatively, during the refresh operation executed a number of timescorresponding to the refresh burst length, the core controller causes,in response to a newly inputted background refresh command, the memorycores within the refresh target banks to successively execute therefresh operation a number of times corresponding to the refresh burstlength, regardless of the remaining number of times of the refreshoperation.

Furthermore, the core controller causes, in response to a refresh-allcommand, the memory cores within the refresh target banks to repeatedlyexecute the refresh operation on the addresses of the refresh addresscounter as well as the remaining addresses.

In the second aspect of the present invention, according to a fourthpreferred embodiment, during the refresh operation performed a number oftimes corresponding to the refresh burst length, the core controllercauses the memory cores within the refresh target banks to stop therefresh operation, in response to a background refresh stop command. Thestop control of the refresh operation is performed so as not to start asubsequent refresh operation after the memory cores within the refreshtarget banks end the refresh operation that is being executed.

In the second aspect of the present invention, according to a fifthpreferred embodiment, on the basis of the setting of an active refreshinterlock flag in the mode register, the background refresh controllersupplies the background refresh control signals to banks other than anaccess target bank corresponding to a bank address to be inputted, inresponse to a normal memory operation command. Accordingly, the memorycontroller can execute the refresh operation on the banks other than theaccess target bank by issuing the normal memory operation commandwithout issuing the background refresh command.

In order to achieve the above object, according to a third aspect of thepresent invention, a memory device has a plurality of banks thatrespectively have memory cores including memory cell arrays and areselected by bank addresses, wherein a memory logical space has aplurality of page areas that are selected by the bank addresses and rowaddresses, and each of the plurality of banks stores two-dimensionallyarrayed data on the basis of a memory mapping in which the plurality ofpage areas are arranged in rows and columns, and in which adjacent pageareas are associated with different bank addresses. The memory devicealso has a control circuit that causes the memory cores within banksselected by the bank addresses to execute normal memory operationcorresponding to a normal operation command in response to the normaloperation command during a period of horizontal access in which thetwo-dimensionally arrayed data is accessed horizontally, and furthercauses a memory core within a refresh target bank other than thehorizontal access target bank to execute refresh operation in responseto a background refresh command. Moreover, during a period ofrectangular access in which an arbitrary rectangular area is accessedfor the two-dimensionally arrayed data, the control circuit causes thememory cores within the banks selected by the bank addresses and withinbanks adjacent to the selected banks, to execute the normal memoryoperation in response to the normal operation command, and prohibits therefresh operation during the normal memory operation.

According to the third aspect described above, the memory deviceperforms the normal memory operation on the selected bank because thenormal memory operation is repeated on a specific bank during thehorizontal access period, and performs the refresh operation on therefresh target bank other than the horizontal access target bank.However, during the rectangular access period, a memory access targetbank cannot be predicted, thus the refresh operation that is performedalong with the normal memory operation is prohibited. Accordingly, thehorizontal access can be continued even during the background refreshoperation, whereby the effective bandwidth can be increased.

In order to achieve the above object, according to a fourth aspect ofthe present invention, the memory system has the memory device of thefirst and second aspects and the memory controller that suppliescommands to the memory device.

In order to achieve the above object, according to a fifth aspect of thepresent invention, the memory controller supplies the commands, refreshbank information, and refresh burst length to the memory device of thefirst and second aspects.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 A figure showing memory mapping of an image memory according tothe present embodiment.

FIG. 2 A figure showing two accesses in the image memory.

FIG. 3 A figure showing a problem of a horizontal access.

FIG. 4 A figure showing a first problem of a rectangular access.

FIG. 5 A figure showing a second problem of a rectangular access.

FIG. 6 A figure showing the entire operation performed in the presentembodiment.

FIG. 7 A figure showing another example of the entire operation of thepresent embodiment.

FIG. 8 A configuration diagram of an image processing system accordingto the present embodiment.

FIG. 9 A configuration diagram of an image memory according to thepresent embodiment.

FIG. 10 A figure for explaining byte boundary functions.

FIG. 11 A timing chart of the byte boundary functions.

FIG. 12 A figure for explaining the byte boundary functions fordifferent mapping.

FIG. 13 A figure for explaining a big endian and little endian shown inFIG. 12.

FIG. 14 A figure for explaining the byte boundary functions in a specialmemory mapping.

FIG. 15 A figure for explaining the special memory mapping shown in FIG.14.

FIG. 16 Timing charts showing the byte boundary functions in arectangular access.

FIG. 17 A configuration diagram of an image processing system forrealizing the byte boundary functions.

FIG. 18 A figure showing the byte boundary functions.

FIG. 19 A configuration diagram of the image processing system thatrealizes simplified byte boundary functions.

FIG. 20 A figure for explaining the image processing system thatrealizes the simplified byte boundary functions shown in FIG. 19.

FIG. 21 A figure showing a schematic configuration of a memory havingthe byte boundary functions.

FIG. 22 A figure showing a first example of the image memory having thebyte boundary functions.

FIG. 23 A figure for explaining the operation shown in FIG. 22.

FIG. 24 A figure showing a second example of the image memory having thebyte boundary functions.

FIG. 25 A figure for explaining the operation shown in FIG. 24.

FIG. 26 A figure showing an operation of a modified example (1) of thesecond example of the image memory having the byte boundary functions.

FIG. 27 A figure showing an operation of a modified example (2) of thesecond example of the image memory having the byte boundary functions.

FIG. 28 A figure showing an operation of a modified example (3) of thesecond example of the image memory having the byte boundary functions.

FIG. 29 A figure showing a third example of the image memory having thebyte boundary functions.

FIG. 30 A figure for explaining the operation shown in FIG. 29.

FIG. 31 A figure showing relation means of input/output terminals of theimage memory having the byte boundary functions.

FIG. 32 A figure showing the operation show in FIG. 31.

FIG. 33 A figure showing relation means for controlling the input/outputterminals of the image memory having the byte boundary functions.

FIG. 34 A figure showing the operation shown in FIG. 33.

FIG. 35 A configuration diagram (1) of the image memory having the byteboundary functions and capable of responding to the endians.

FIG. 36 A configuration diagram (2) of the image memory having the byteboundary functions and capable of responding to the endians.

FIG. 37 A configuration diagram (3) of the image memory having the byteboundary functions and capable of responding to the endians.

FIG. 38 An operation timing chart of the up mode of a DDR memory shownin FIG. 37.

FIG. 39 An operation timing chart of the down mode of the DDR memoryshown in FIG. 37.

FIG. 40 A figure for explaining a method of designating a boundary ofthe byte boundary functions.

FIG. 41 A figure for showing a conversion circuit of a start byte SB anda shift value SV.

FIG. 42 A figure for explaining an automatic rectangular access usingthe byte boundary functions.

FIG. 43 A timing chart of an automatic rectangular access.

FIG. 44 A configuration diagram of an internal column address calculatorthat is required in the automatic rectangular access.

FIG. 45 A figure showing an example of memory operation performed whenan access made by the byte boundary functions reaches the end of a pagearea.

FIG. 46 A figure showing another example of the memory operationperformed when an access made by the byte boundary functions reaches theend of a page area.

FIG. 47 A figure showing yet another example of the memory operationperformed when an access made by byte the boundary functions reaches theend of a page area.

FIG. 48 A figure for explaining other application of the byte boundaryfunctions.

FIG. 49 A figure for explaining other application of the byte boundaryfunctions.

FIG. 50 A figure for explaining other application of the byte boundaryfunctions.

FIG. 51 A configuration diagram of the image processing system.

FIG. 52 A figure showing input and output signals of a memorycontrolling section (memory controller).

FIG. 53 A figure for explaining a reference image area, which is atarget of reading within a frame image.

FIG. 54 A detailed configuration diagram of the memory controller.

FIG. 55 A figure for explaining computation performed by the interprediction section 513 in the reference image reading controller 514.

FIG. 56 A figure showing an example of computation performed by theinter prediction section 513 in the reference image reading controller514.

FIG. 57 A figure showing an example of memory mapping.

FIG. 58 A figure showing a configuration of the page area 14 in thememory mapping 12.

FIG. 59 A figure showing an arrangement of the reference image areas onthe memory map, the reference image areas being shown in FIG. 56.

FIG. 60 A figure showing an example of another arrangement of thereference image areas on the memory map.

FIG. 61 A timing chart of the memory controller with respect to thememory without the byte boundary functions.

FIG. 62 A timing chart of the memory controller with respect to thememory having the byte boundary functions.

FIG. 63 A timing chart of the memory controller with respect to thememory without the byte boundary functions and the multi-bank accessfunction.

FIG. 64 A timing chart of the memory controller with respect to thememory having the multi-bank access function and the byte boundaryfunctions.

FIG. 65 A flowchart of the control operation of the memory controller.

FIG. 66 A flowchart of the control operation of the memory controller.

FIG. 67 A schematic explanatory diagram for explaining a multi-bankaccess according to the present embodiment.

FIG. 68 A figure for explaining the multi-bank access according to thepresent embodiment.

FIG. 69 A timing chart showing the case in which the multi-bankinformation SA′ is the bank number information (=4).

FIG. 70 A timing chart showing the case in which the multi-bankinformation SA′ is the size information of a rectangular area (W=8bytes, H=8 rows).

FIG. 71 A configuration diagram of the memory device having themulti-bank access function.

FIG. 72 A figure showing a first example of the multi-bank activationcontroller 88.

FIG. 73 A figure showing the first example of the multi-bank activationcontroller 88.

FIG. 74 A figure showing a second example of the multi-bank activationcontroller 88.

FIG. 75 A figure showing the second example of the multi-bank activationcontroller 88.

FIG. 76 A figure showing a third example of the multi-bank activationcontroller 88.

FIG. 77 A figure showing the third example of the multi-bank activationcontroller 88.

FIG. 78 A figure showing Example 1 of bank activation timing.

FIG. 79 A figure showing Example 2 of bank activation timing.

FIG. 80 A figure for explaining the logic of the bank activation timingcontrol performed by the activating bank control circuit 88C.

FIG. 81 A figure showing Example 3 of the bank activation timing.

FIG. 82 A figure for explaining generation of row addresses in themulti-bank access according to the present embodiment.

FIG. 83 A figure showing Example 1 of the row address computer accordingto the present embodiment.

FIG. 84 A figure showing Example 2 of the row address computer accordingto the present embodiment.

FIG. 85 A figure showing two examples of memory mapping.

FIG. 86 A figure showing the bank address switching circuit 861 for twotypes of memory mapping described above.

FIG. 87 A figure showing a timing chart showing the case in whichmulti-bank access and byte boundary are generated.

FIG. 88 A configuration diagram of the memory device having themulti-bank access function and byte boundary function.

FIG. 89 A figure showing an example of memory mapping.

FIG. 90 A configuration diagram of the memory controller according tothe present embodiment.

FIG. 91 A figure showing signals between the access source blocks andthe interfaces.

FIG. 92 A figure for explaining the data on the access target area.

FIG. 93 A timing chart of the signals between the access source blocksand the interfaces.

FIG. 94 A figure showing schematic operation of the memory controller.

FIG. 95 A configuration diagram of the sequencer SEQ.

FIG. 96 A figure for explaining the computing equation used forgenerating the intermediate parameters.

FIG. 97 An operational flowchart of the command/address generatingsection.

FIG. 98 A timing chart between the memory controller and the memorydevice.

FIG. 99 A schematic explanatory diagram of the background refresh in thepresent embodiment.

FIG. 100 A schematic explanatory diagram of the memory system in whichthe background refresh of the present embodiment is performed.

FIG. 101 An operational flowchart of the memory controller forcontrolling the background refresh.

FIG. 102 A figure showing a relationship between the background refreshand horizontal access according to the present embodiment.

FIG. 103 A figure showing a relationship of the background refresh tohorizontal accesses and rectangular access according to the presentembodiment.

FIG. 104 A figure for explaining the number of times and the number ofblocks the background refresh is performed according to the presentembodiment.

FIG. 105 A timing chart of the background refresh operation according tothe present embodiment.

FIG. 106 A figure for explaining the refresh burst length according tothe present embodiment.

FIG. 107 A figure for explaining the refresh burst length according tothe present embodiment.

FIG. 108 A configuration diagram of the entire memory device having thebackground refresh function.

FIG. 109 A configuration diagram of the banks of the memory devicehaving the background refresh function.

FIG. 110 A configuration diagram of the banks of the memory devicehaving the background refresh function.

FIG. 111 Another configuration of the banks of the memory device.

FIG. 112 A figure for explaining the background refresh operationaccording to the present embodiment.

FIG. 113 A figure showing circuits of first and second refresh bankdecoders.

FIG. 114 A figure showing a circuit of a third refresh bank decoder.

FIG. 115 A figure showing a circuit of a fourth refresh bank decoder.

FIG. 116 A figure showing a circuit of a fifth refresh bank decoder.

FIG. 117 A figure showing a circuit of a sixth refresh bank decoder.

FIG. 118 A figure showing a circuit of a seventh refresh bank decoder.

FIG. 119 A configuration diagram of the core control circuit.

FIG. 120 A timing chart showing an operation of the core controlcircuit.

FIG. 121 A figure showing a configuration and an operation of theaddress latch circuit.

FIG. 122 A timing chart showing a refresh burst operation.

FIG. 123 A configuration diagram of the core control circuit thatcontrols the refresh burst operation.

FIG. 124 Another configuration diagram of the core control circuit thatcontrols the refresh burst operation.

FIG. 125 A detailed circuit diagram of the timing control circuit 1190and of the refresh control circuit 1191 within the core control circuit.

FIG. 126 Another detailed circuit diagram of the timing control circuit1190 and of the refresh control circuit 1191 within the core controlcircuit.

FIG. 127 A configuration diagram showing the refresh burst lengthcounter 1230, refresh burst length register 1231, and refresh burst enddetection circuit 1232.

FIG. 128 A configuration diagram of the address latch circuit.

FIG. 129 A timing chart of the refresh burst operation.

FIG. 130 A figure showing an overview of refresh burst stop operation.

FIG. 131 A configuration diagram of the core control circuit having therefresh burst stop function.

FIG. 132 A circuit diagram of the refresh state control circuit.

FIG. 133 A circuit diagram of the timing control circuit 1190 and of therefresh control circuit 1191 of the core control circuit.

FIG. 134 Another circuit diagram of the timing control circuit 1190 andof the refresh control circuit 1191 of the core control circuit.

FIG. 135 A timing chart showing an operation of FIG. 133.

FIG. 136 A circuit diagram of the command decoder that realizes therefresh stop function.

FIG. 137 A configuration diagram of the core control circuit 1085 thatperforms countdown refresh burst control.

FIG. 138 A truth table showing a relationship between a refresh burstlength set in the refresh burst length register 1231 and the addressterminals A<3:0>.

FIG. 139 Another configuration diagram of the core control circuit 1085that performs the countdown refresh burst control.

FIG. 140 A circuit diagram of the timing control circuit 1190 and of therefresh control circuit 1191 within the core control circuit 1085.

FIG. 141 A circuit diagram of the refresh burst length register 1231 andof the refresh burst length counter 1230.

FIG. 142 A circuit diagram of the refresh burst length register 1231 andof the refresh burst length counter 1230.

FIG. 143 A circuit diagram of the refresh address counter 1083 and ofthe refresh address comparison circuit 1370.

FIG. 144 A timing chart showing the case in which the RBL of thecountdown core control circuit is 3.

FIG. 145 A timing chart of a refresh stop operation performed by thecountdown core control circuit.

FIG. 146 A timing chart of the refresh stop operation of the countdowncore control circuit.

FIG. 147 A timing chart showing the refresh-all operation of thecountdown core control circuit.

FIG. 148 A timing chart showing an operation for resetting the refreshcommand, the operation being performed by the countdown core controlcircuit.

FIG. 149 A timing chart showing an operation for resetting the refreshcommand, the operation being performed by the countdown core controlcircuit.

FIG. 150 A timing chart showing the active and refresh interlockingcontrol.

FIG. 151 A circuit diagram of the refresh bank decoder in the active andrefresh interlocking control.

FIG. 152 A circuit diagram of the core control circuit in the active andrefresh interlocking control.

FIG. 153 A circuit diagram of the address latch circuit in the activeand refresh interlocking control.

FIG. 154 A configuration diagram of a bank circuit.

FIG. 155 A figure showing control of the memory block within the corecorresponding to the refresh block count.

FIG. 156 A circuit diagram of the address latch circuit.

FIG. 157 A circuit diagram of a predecoder circuit within the rowdecoder.

FIG. 158 A configuration diagram of a memory system having thebackground refresh function.

FIG. 159 A figure showing an example of memory mapping.

FIG. 160 A figure showing a front pixel address and the size informationin a horizontal access and a rectangular access.

FIG. 161 A configuration diagram of the memory controller.

FIG. 162 A timing chart of the operation of the memory controller.

FIG. 163 A table for explaining the decoder DEC0 and selector SEL0 ofthe active bank number generating section.

FIG. 164 A table for explaining the meanings of values 000b through 111bthat can be set to ACTBL of the register 543.

FIG. 165 A figure showing a conversion table of the decoder DEC1.

FIG. 166 A table showing a conversion operation performed by the decoderDEC1 corresponding to a first example of the register set values.

FIG. 167 A table showing a conversion operation of the decoder DEC1corresponding to a second example of the register set values.

FIG. 168 A table showing an operation of the selector SEL1.

FIG. 169 A table showing a conversion table of the decoder DEC2.

FIG. 170 A figure showing an operation of the decoder DEC2 in the caseof the first register set value.

FIG. 171 A figure showing an operation of the decoder DEC2 in the caseof the second register set value.

FIG. 172 A figure showing an operation of the decoder DEC2 in the caseof the third register set value.

FIG. 173 A figure showing an operation of the decoder DEC2 in the caseof the fourth register set value.

FIG. 174 A figure showing a start byte signal SB in a byte boundary.

FIG. 175 A figure showing a relationship between second information BMRand first information SB of the byte combination data (start byte).

FIG. 176 A figure showing the row address step RS.

FIG. 177 A figure showing the memory mapping information AR.

FIG. 178 A figure showing the refresh burst length RBL and the refreshblock count RBC in a background refresh.

FIG. 179 A figure showing a configuration of the special input terminal,an input buffer thereof, and a mode register within the memory device.

FIG. 180 A figure showing a configuration of the special input terminal,input buffer thereof, and mode register within the memory device.

FIG. 181 A figure showing an example of the mode register.

FIG. 182 A figure showing an example of an enable signal generatingcircuit.

FIG. 183 A figure showing an input method in a single data rate (SDR).

FIG. 184 A figure showing an input method in a double data rate (DDR).

FIG. 185 A figure showing an input method using an ADQ multiplex inputsystem.

FIG. 186 A figure showing an in input method using an address multiplexinput system.

FIG. 187 A figure showing the input method using the address multiplexsystem in the double data rate (DDR)

FIG. 188 A figure showing the input method using the address multiplexsystem in the double data rate (DDR).

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiments of the present invention are described with reference to thedrawings. However, the technical field of the present invention is notlimited to these embodiments, and thus covers the matters described inthe patent claims and equivalents thereof.

[Memory Mapping of Image Memory, and Problems involved in the MappingMemory]

FIG. 1 shows memory mapping of an image memory according to the presentembodiment. In FIG. 1, display image data in an image processing systemhaving a display device 10 is stored in image memory 15. The displayimage data is constituted by data on a luminance signal Y andcolor-difference signals Ca and Cb of each pixel and RGB gradationsignals of each pixel, wherein each signal is constituted by data of,for example, 8 bits (1 byte).

Meanwhile, the image memory 15 is generally constituted by ahigh-capacity and high-speed semiconductor memory device in which anintegrated circuit is formed on a semiconductor substrate such as SDRAM.Such image memory is constituted by a plurality of banks Bank 0 through3 (four banks as shown in FIG. 1), wherein each Bank 0-3 has a pluralityof blocks BLK-0, and each of the blocks has a plurality of word linesWL, bit lines BL, and memory cells MC which are at the intersections ofthe word lines and bit lines. Each memory cell is constituted by anunshown MOS transistor of which gate is connected to a word line, and acapacitor that is connected to the transistor. In the example shown inFIG. 1, the four banks are associated with bank addresses BA 0 through 3respectively, the word lines are associated with row addresses RA 0through 7, and the bit lines are associated with column addresses CA 0through 127. A word line within a bank is selected by a combination of abank address BA and a row address RA, and a bit line is selected by acolumn address CA. 4 bytes of data items, BY 0 through 3, are accessedby the bank address BA, row address RA and column address CA. Since 1byte consists of 8 bits, 4 bytes of data items, i.e., 4×8=32 bits ofdata, are associated with an input/output terminals of the memory at oneaccess, and then reading or writing is performed. Generally, theabovementioned 1 byte of data (8 bits of data) corresponds to a signalof a pixel. By inputting/outputting 4 bytes of data items at one access,a bandwidth, which indicates the number of pixels that can be processedper unit time with respect to the image data, can be increased.

According to the memory mapping 12 for the display image data, pageareas 14, each of which is specified by the bank address BA and rowaddress RA, are placed in rows and columns. As shown in an enlarged area14E, one page area 14 has 128 memory unit areas that are specified bythe column addresses CA0 through 127, and each of the memory unit areasstores the 4 bytes of data items, BY 0 through 3. The 4 bytes of dataitems, BY 0 through 3, are inputted/outputted via a total of 32input/output terminals of a memory, i.e., via input/output terminals DQ0 through 7, DQ 8 through 15, DQ 16 through 23, and DQ 24 through 31.8-bit data of each byte corresponds to signal data of a pixel.

The memory map 12 is suitable for operating, at high speed, the imagememory 15 such as the SDRAM constituted by a plurality of banks. Inresponse to an active command provided along with both the bank addressBA and the row address RA, the SDRAM performs the active operation thatdrives the selected word line within the selected bank, reads the datastored in a memory cell into the bit line, activates the sense amplifierassociated with the bit line to amplify the bit line potential, andthereafter, in response to a read command provided along with the columnaddress CA, performs the read operation for reading the data from theselected bit line. Alternatively, after performing the active operationthe SDRAM responds to a write command provided along with the columnaddress CA and write data, to perform the write operation for writingthe write data into the selected bit line. Precharge operation using aprecharge command is performed after the read operation or the writeoperation, and then the active operation and the read or write operationare performed again. In this manner, in the SDRAM each bank canindependently perform the active operation, read operation and writeoperation.

According to the memory map 12 shown in FIG. 1, different bank addressesBA 0 through 3 are assigned to the page areas 14 that are vertically andhorizontally adjacent to each other. Specifically, bank addresses BA 0and 1 are alternately arranged in the odd-numbered rows in the memorymap 12, while bank addresses BA 2 and 3 are alternately arranged in theeven-numbered rows. Moreover, the row addresses RA 0 through 7 arerepeatedly incremented by two in the raster direction (row direction) ofthe memory map 12, and each of the rows in the memory map 12 is wrappedafter every four row addresses RA 0 through 3 and RA 4 through 7.

By adopting the memory mapping for allocating the page areas on an imagewithout causing the page areas having the same bank to be adjacent toeach other in the row direction or the column direction, the horizontalaccess that is a representative access made to the image memory, i.e.,the access in which the page areas 14 are moved in the row direction andone page area is selected, can be made to the image memory, while theactive operation and the read/write operation are executedsimultaneously by using two banks, whereby the access efficiency can beimproved. The same is true for the case where the image memory isaccessed in a vertical direction.

FIG. 2 shows two accesses in the image memory. The horizontal accessshown in FIG. 2(A) is an access that occurs mostly wheninputting/outputting a video frame image, and corresponds to rasterscanning for accessing the image in a horizontal direction 20 from theupper left to the lower right. On the other hand, the rectangular accessshown in FIG. 2(B) is an access that occurs mostly when compressing orexpanding an MPEG image or the like, and corresponds to an operation foraccessing the image from the upper left to the lower right in adirection of an arrow 24 within a rectangle 22 with an arbitrary aspectratio. The rectangular area 22 corresponds to a block or the like thatis a target for extracting a motion vector of the MPEG image.

Generally, in an image system using an image memory, the transfer rateof transferring the image memory, which is a frame memory, is set fasterthan the speed of image display operation, so that, while the image dataread by horizontally accessing the image memory is displayed on ascreen, new frame data is created by means of the rectangular access,and that frame data is continuously created and outputted. Therefore,both horizontal access and rectangular access are made in an actualimage system.

In the horizontal access, scanning is performed in the horizontaldirection 20, thus memory access can be made efficiently, whileactivating adjacent banks simultaneously. In the rectangular access, onthe other hand, the position of the rectangular area 22 to be accessedis not caused to go beyond a single bank and a page area within thebank, whereby the data within the rectangular area 22 can be accessed byperforming single active operation for specifying the bank address BAand the row address RA, thus efficient memory access can be performed,as with the horizontal access.

FIG. 3 shows a problem of the horizontal access. There is shown a timingchart 30 of the horizontal access made in the horizontal direction 20 inthe abovementioned memory map 12. In this timing chart, an automaticrefresh command AREF is generated when horizontally accessing (20 in thefigure) the page area in the fourth row of the memory map 12 (BA 0/RA 4,BA 1/RA 4, BA 0/RA 5, BA 1/RA 5). The timing chart 30 shows a commandCMD, clock CLK, bank address BA, row address RA, column address CA, andinput/output terminals DQ.

A burst length BL is set to 4 as a premise. When the active operation isperformed on the page area with BA 0/RA 4 by an active command ACT 32and an instruction is issued by a read command RD 33 to read the pagearea with BA 0/CA 0, four 32-bit data items are successively outputtedfrom the input/output terminals DQ in four clock cycles after apredetermined latency (four clock in the figure). Specifically, each ofthe four 32-bit data items in the respective column addresses CA 0through 3 within the page area BA 0/RA 4 is outputted four timessuccessively. This burst operation is required to the SDRAM as astandard. The above-described operation suggests that each 4 byte(32-bit) data item of each of the column addresses CA 0 through 3 withinthe page area 14E enlarged in FIG. 1 is outputted four timessuccessively.

Next, 4 bytes of data items of the page area BA 1/RA 4 are outputted bymeans of an active command ACT 34 and a read command RD 35. Similarly, 4bytes of data items of the page area BA 0/RA 5 are outputted by means ofan active command ACT 36 and a read command RD 37, and 4 bytes of dataitems of the page area BA 1/RA 5 are outputted by means of an activecommand ACT 38 and a read command RD 39.

At this point, when an automatic refresh command AREF 40 for specifyinga row address RA 6 is generated, the SDRAM memory configuring the imagememory executes a refresh operation on all incorporated banks, i.e.,four banks BA 0 through 3, in parallel. Specifically, the word lines ofthe respective row addresses RA 6 within the respective four banks aredriven simultaneously, the corresponding sense amplifiers are activated,rewriting is performed, and then the precharge operation is performed.This refresh operation is performed on four page areas 31 within thememory map 12 shown in FIG. 3. Therefore, the horizontal access (arrow20) is stopped temporarily during a refresh operation period tREF. Afterthe refresh operation period tREF, the next page area BA 0/RA 6 isaccessed again by means of an active command ACT 41 and a read commandRD (not shown), whereby the horizontal access is restarted.

Since the refresh operation is performed for four banks simultaneouslyby means of the refresh command AREF, the horizontal access is stoppedtemporarily when the refresh command is generated while the horizontalaccess is made, thus the effective bandwidth becomes narrow. This is theproblem occurring in the horizontal access.

FIG. 4 shows a first problem of the rectangular access. FIG. 4(A) showsan example of the horizontal access, and FIG. 4(B) shows an example ofthe rectangular access. Both examples are the accesses exceeding theboundary of a memory unit area (4-byte area) 45 selected by a columnaddress CA. As described above, according to a generally-known memorymap, the page area 14 that is specified by a bank address BA and a rowaddress RA is sectioned into a plurality of memory unit areas 45selected by the column addresses CA 0 through 127, and 4 bytes of dataitems BY 0 through 3 are accessed simultaneously by a single columnaddress CA. 8-bit data of each byte corresponds to a signal of a pixel.

Therefore, although the horizontal access is made relativelyeconomically, unnecessary input/output of data occurs in the rectangularaccess, thus the effective bandwidth decreases.

In the horizontal access shown in FIG. 4(A), when accessing an area 22A,four read commands RD are issued for the column addresses CA 0 through 3subsequent to the active command ACT for specifying the page area BA0/RA 0, and 4 bytes of data items BY 0 through 3 of each of the columnaddresses CA 0 through 3 are inputted/outputted successively. In thiscase, the area 22A contains a section from bytes BY 2 and 3 of thecolumn address CA 0 to bytes BY 0 and 1 of the column address CA 3.Therefore, of the input/output DQ of 4 bytes of data corresponding tothe column address CA 0, the data items of the bytes BY 0 and 1 are notrequired, and, of the input/output DQ of 4 bytes of data correspondingto the column address CA 3, the data items of the bytes BY 2 and 3 alsoare not required. Therefore, the volume of the effective output data is12 bytes/16 bytes.

On the other hand, in the rectangular access shown in FIG. 4(B), whenaccessing a rectangular area 22B, six read commands RD are issued forthe column addresses CA 0, 1, 4, 5, 8 and 9 subsequent to the activecommand ACT for specifying the page area BA 0/RA 0, and 4 bytes of dataitems BY 0 through 3 of each of the column addresses CA 0 1, 4, 5, 8 and9 are inputted/outputted successively. However, the rectangular area 22Bdoes not match with the boundary of the memory unit area (4-byte area)45 selected by the column addresses and exceeds the boundary of the4-byte area, thus half of each of the 4-byte data items BY 0 through 3is unnecessary data. Specifically, the volume of the effective outputdata is 12 bytes/24 bytes. FIG. 4(B) shows the worst case.

As described above, even if the data to be accessed has the same numberof bytes, in the rectangular access 24 bytes of data need to beinputted/outputted by sending the read command RD six times, but in thehorizontal access 16 bytes of data may be inputted/outputted by sendingthe read command RD four times. Therefore, in the rectangular accessthat exceeds the boundary of the 4-byte area (memory unit area) 45selected by a single column address, the effective bandwidth decreases.This is the first problem of the rectangular access.

FIG. 5 shows a second problem of the rectangular access. The rectangularaccess is an access made to an arbitrary rectangular area and sometimesexceeds a boundary 14BOU of adjacent page areas 14. FIG. 5 shows a casein which a rectangular area 22(A) is a 16-byte area within the same pagearea BA 1/RA 6, and a case in which a rectangular area 22(B) is a16-byte area covering four adjacent page areas BA 3/RA 2, BA 2/RA 3, BA1/RA 6 and BA 0/RA 7.

In the case of the rectangular area 22(A), 16 bytes of data can beinputted/outputted by issuing an active command ACT (50 in the figure)once for the page area BA 1/RA 6 and a read command RD (52 in thefigure) four times for the column addresses CA 6, 7, 10 and 11, as shownin the timing chart.

In the case of the rectangular area 22(B), on the other hand, 16 bytesof data cannot be inputted/outputted unless an active command ACT (54 inthe figure) is issued four times for the page areas BA 3/RA 2, BA 2/RA3, BA 1/RA 6 and BA 0/RA 7 and unless a read command RD (56 in thefigure) is issued four times for the column addresses CA 127 (BA 3), CA124 (BA 2), CA 3 (BA 1) and CA 0 (BA 0), as shown in the timing chart.Specifically, in the case where the rectangular area 22 includesadjacent page areas, the active commands ACT are issued a number oftimes in order to perform the active operation on different banks, andthe read commands RD or write commands WR have to be issued for thecolumn addresses within the respective banks. Therefore, the amount ofdata that can be accessed per unit time is reduced, and the effectivebandwidth is narrowed.

In the case where the rectangular area 22(B) shown in FIG. 5 issectioned at the middle of the memory unit area (4-byte area) selectedby a column address, the first problem illustrated in FIG. 4 occurs atthe same time, thus a plurality of active commands are required (secondproblem), and unnecessary data is contained in the input/output data DQcorresponding to the read commands (first problem), causing decrease ofthe effective bandwidth.

As described above, in the case of adopting the memory mapping, thatutilizes the structural characteristics of the SDRAM, in the imagememory, there are the first problem in which the horizontal access isstopped due to the occurrence of the refresh command when the horizontalaccess is performed, the second problem in which unnecessaryinput/output data is generated when the rectangular access area exceedsthe boundary of the memory unit area (4-byte area) selected by a columnaddress, and a third problem in which a plurality of bank activecommands are required to be issued when the rectangular access areaexceeds the boundary of the page areas specified by the bank addresses.

GENERAL DESCRIPTION OF THE PRESENT EMBODIMENT

Hereinafter, configurations and operations for solving these problemsare described briefly.

The present embodiment is to solve the discontinuation of the accessthat is caused by the refresh operation, the decrease of the accessefficiency that is caused by the rectangular access, and other problems,wherein, first of all, the refresh operation can be performed in thebackground along with an access operation at the time of the horizontalaccess, secondly, at the time of the rectangular access, a function ofefficiently accessing an area straying from or exceeding the memory unit(4-byte area) selected by a column address is made possible, and,thirdly, a function of efficiently accessing a rectangular areaexceeding the boundary of the page areas and containing a plurality ofpage areas is made possible.

FIG. 6 shows the entire operation performed in the present embodiment.As described above, in an image system utilizing an image memory, boththe horizontal access and the rectangular access are generated. Theexample shown in FIG. 6 is an example in which a horizontal access 20-1to page areas with the bank addresses BA 0 and BA 1 in the first row ofthe memory map 12, a rectangular access 22 to a page area BA 2/RA 2 inthe second row, and a horizontal access 20-2 to page areas with the bankaddresses BA 2 and BA 3 in the second row are generated sequentially. Inthe rectangular access 22, access is made to a rectangular areaexceeding the memory unit area (4-byte area) 45 within one page area BA2/RA 2.

In this case, in the rectangular access, access is generated in anarbitrary bank of the memory, while, in the horizontal access, access isgenerated only in a predetermined bank for a certain period of time. Forexample, in the horizontal access in the first row of the memory map 12,access is generated only in the banks BA 0 and 1, and no access isgenerated in the banks BA 2 and 3 in the second row. On the other hand,in the horizontal access in the second row, access is generated only inthe banks BA 2 and 3, and no access is generated in the banks BA 0 and 1in the first row.

Therefore, in the horizontal access 20-1, a background refresh commandBREN for specifying a bank in which no access is generated for some timeto come is issued before memory access is made, and information of thebank in which no access is generated, SA=2/3, is notified to the memory.Specifically, subsequent automatic refresh operation is allowed in thebank SA specified by the background refresh command BREN. Therefore,normal access is not allowed to the bank SA=2, 3 to which the refreshoperation is applied.

In the horizontal access 20-1 shown in FIG. 6, refresh bank informationSA (61 in the figure) for allowing subsequent refresh operation to beperformed is issued along with the background refresh command BREN (60in the figure), thereafter the active operation is performed on the pagearea BA 0/RA 0 by means of the active command ACT, and then 4 bytes ofdata items BY 0 through 3 of the column address CA 0 are outputted tothe input/output terminal DQ by the read command RD (BA 0, CA 0).Similarly, the active operation is performed on the page area BA 1/RA 0by means of the active command ACT, and then 4 bytes of data items BY 0through 3 of the column address CA 0 are outputted to the input/outputterminal DQ by the read command RD (BA 1, CA 0). However, FIG. 6 omitsthe illustration of output of four 4-byte data items corresponding toBL=4.

During the period of this horizontal access 20-1, when an automaticrefresh request (not shown), which is activated by the backgroundrefresh command BREN within the image memory, is issued, the refreshoperation is started on the banks BA 2 and 3. However, in the horizontalaccess, access is generated only in the banks BA 0 and 1 and differentbanks can independently perform the active operation in the SDRAM, thusthe horizontal access can be prevented from being disturbed and stoppedby the refresh operation performed on the banks BA 2 and 3.

Next, in the rectangular access shown in FIG. 6, the rectangular area 22is in the same page area BA2/RA2 and contains 2 bytes, BY 2 and 3, i.e.,the second half of the column address CA 0, and 2 bytes, BY 0 and 1,i.e., the first half of the column address CA 1. In this case, accordingto a general read command of the SDRAM, a read command RD needs to beissued twice to the column addresses CA 0 and 1.

However, in the present embodiment, a read command RD (62 in the figure)is issued to the column address CA 0 (63 in the figure), and bytecombination information SB (64 in the figure) on the access is supplied,whereby 4 bytes corresponding to the byte combination information SB canbe automatically associated with the input/output terminal DQ. In theexample described above, byte shift information SB=2, which means thebytes following 2 bytes, is specified as the byte combinationinformation SB, whereby, out of the 4 bytes of data items of the columnaddress CA 0, the data items of the bytes BY 2 and 3 subsequent to the 2bytes are automatically outputted along with the data items of the firsttwo bytes BY 0 and 1 of the 4 bytes of data items of the adjacent columnaddress CA 1.

In the rectangular access shown in FIG. 6, after the active command ACTfor the page area BA 2/RA 2 is issued, the read command RD 62 forspecifying BA 2/CA 0 (63 in the figure) is issued along with the bytecombination information SB=2 (64 in the figure). This byte combinationinformation SB=2 indicates a combination of 4 bytes of data itemsincluding the byte BY 2 that follows the first 2 bytes within the 4-bytearea. In other words, this byte combination information SB=2 indicatesthat the first byte position (start byte) of the 4-byte area is the BY2. In response to this, the image memory associates the data items ofthe bytes BY 2 and 3 following the first 2 bytes (or from the start byteBY 2) of the 4 bytes of data items of the column address CA 0, and thedata items of the bytes BY 0 and 1 of the column address CA 1, with the4 bytes of input/output terminals DQ, for outputting thereto. The memorycontroller does not need to issue the read command RD twice to thecolumn addresses CA 0 and 1. Moreover, only required data is outputtedto all of the 4 bytes of input/output terminals DQ, thus unnecessarydata is not outputted, and the access efficiency improves.

Furthermore, when the read command RD specifying BA 2/CA 4 is issuedalong with the combination information SB=2, the image memory outputs 4bytes of data constituted by 2 bytes of data of column addresses CA 4and 5. When the read command RD specifying BA 2/CA 8 is issued alongwith the combination information SB=2, the image memory outputs 4 bytesof data constituted by 2 bytes of data of column addresses CA 8 and 9.When the read command RD specifying BA 2/CA 12 is issued along with thecombination information SB=2, the image memory outputs 4 bytes of dataconstituted by 2 bytes of data of column addresses CA 12 and 13.

As a result, even if the rectangular access area 22 includes the memoryunit areas (four byte areas) of the eight column addresses CA 0, 1, 4,5, 8, 9, 12 and 13, it is only necessary to issue the read command RD tothe column addresses CA 0, 4, 8 and 12 four times, and unnecessary datais not outputted to the input/output terminals, thus the accessefficiency can be improved by two times.

In the horizontal access 20-2 subsequent to the rectangular access,since the page areas in the second row of the memory map 12 areaccessed, thus normal access is not generated in the banks BA 0 and 1for awhile. Therefore, as with the above explanation, SA=1 is specifiedalong with the background refresh command BREN (65 in the figure) as thebank information SA on a bank (66 in the figure) in which the freshoperation can be performed, and the automatic refresh operation isallowed in the banks BA 0 and 1 in parallel with normal access to thesubsequent banks BA 2 and 3.

As described above, the horizontal accesses 20-1 and 20-2 allow theautomatic refresh operation in the background when normal access ismade, but the rectangular access does not allow the automatic refreshoperation in the background. As a result, in the horizontal access 20-1,the normal access operation can be performed in the banks BA 0 and 1 inparallel with the refresh operation in the banks BA 2 and 3, and in thehorizontal access 20-2, the normal access operation can be performed inthe banks BA 2 and 3 in parallel with the refresh operation in the banksBA 0 and 1. Accordingly, the horizontal accesses can be prevented frombeing disturbed by the refresh operation, and the effective bandwidthcan be prevented from decreasing.

Furthermore, in the rectangular access, the background refresh operationis prohibited. Accordingly, the rectangular access made to an arbitraryarea can be prevented from being stopped by the refresh operation.Therefore, the effective bandwidth can be totally prevented fromdecreasing.

Also, in the rectangular access, the byte combination information SB isspecified along with the read command, whereby combined byte data, whichis obtained by combining arbitrary bytes with a column address CA of theread command as a start area, can be outputted to the 4 bytes ofinput/output terminals DQ. The byte combination information SB can alsobe specified along with a command for setting a mode register in advanceof the active command.

FIG. 7 shows another example of the entire operation of the presentembodiment. This example is an example in which the horizontal access20-1 to page areas in the first row of the memory map, the rectangularaccess 22, and the horizontal access 20-2 to page areas in the secondrow of the memory map are performed sequentially. In the rectangularaccess 22, the rectangular area 22 exceeds the boundary 14BOU of thepage areas and contains four page areas BA 3/RA 2, BA 2/RA 3, BA 1/RA 6and BA 0/RA 7.

As with FIG. 6, in the horizontal accesses 20-1 and 20-2, the refreshbank information SA is issued along with the background refresh commandBREN, whereby subsequent automatic refresh operation is allowed in thesubject banks, and the horizontal accesses are prevented from beingdisturbed by the refresh operation. In the rectangular access to therectangular area 22 having a plurality of areas, i.e. a plurality ofbanks, multi-bank information SA′ is issued along the active commandACT, as bank information on the banks that are subjected to the activeoperation simultaneously. In response to this, the image memory,performs the active operation on the page areas of the plurality ofbanks specified by the multi-bank information SA′ and having upper leftbank of address information BA, RA issued along with the active commandACT, simultaneously. As a result, in response to one active command ACT,the active operation can be performed on the plurality of bankssimultaneously. Thereafter, the read command RD for each bank is issuedalong with the bank address BA and column address CA, whereby four bankdata items of a memory unit area (4 bank area) selected by the columnaddress CA of each bank can be outputted to the input/output terminalsDQ.

In the example of the rectangular access shown in FIG. 7, addressinformation items BA 3 and RA 2 (71 in the figure) for specifying thepage areas in the upper left section are issued along with an activecommand ACT (70 in the figure), and at the same time the multi-bankinformation SA′=0-3 (72 in the figure) is issued. In response to this,the image memory, performs the active operation on four banks BA 3, BA2, BA 1 and BA 0 simultaneously, the four banks being specified by themulti-bank information SA′, placing a bank BA 3 of the upper-left pagearea in front and sequentially outputs 4 bytes of data items of thebanks BA/columns CA that are specified by the subsequent four readcommands RD. The same applies to the write command. In the figure, BA3/CA 127, BA 2/CA 124, BA 1/CA 3, and BA 0/CA 0 are supplied in responseto the four read commands, and 4 bytes of data items of these memoryareas are outputted.

If the multi-bank information SA′ indicates “two banks in the lateraldirection”, a bank on the right side of an upper left bank correspondingto the bank address BA supplied by the active command ACT is alsosubjected to the active operation simultaneously. If the multi-bankinformation SA′ indicates “two banks in the vertical direction”, a bankthat is located below the upper left bank is also subjected to theactive operation simultaneously. Similarly, if the multi-bankinformation SA′ indicates “four banks in the lateral and verticaldirections”, four banks that are located on the right side, below, andon the lower right side of the upper left bank are also subjected to theactive operation simultaneously. Therefore, in order to perform theactive operation automatically on multiple banks, it is preferred topreviously set, in the register or the like, information indicating howthe row addresses RA in the respective rows of the memory map arearranged, or indicating, specifically, in what unit the row addresses RAare wrapped (row address step information).

In the rectangular access method shown in FIG. 7, when the bytecombination information SB described in FIG. 6 is issued along with theread command RD in addition to the multi-bank information SA′ at theactive command ACT, a partial byte combination of the memory unit areas(four bank areas) exceeding the boundary 14BOU of a page area 14 andselected by a column address CA can be associated automatically with theinput/output terminals DQ.

FIG. 8 is a configuration diagram of an image processing systemaccording to the present embodiment. The image processing system isconstituted by an image processing chip 80 corresponding to the memorycontroller, and an image memory chip 86 for storing image data which isa target of image processing. The image processing chip 80 and thememory chip 86 are each a semiconductor chip wherein an integratedcircuit is formed on a single semiconductor substrate.

The image processing chip 80 has: an image processing controller 81 forperforming image processing, such as an encoder or decoder that respondsto image compression and expansion of, for example, MPEG; and a memorycontroller 82 for controlling an access to the image memory chip 86 inresponse to a memory access request that includes image areaspecification issued from the image processing controller 81. The memorycontroller 82 has: a background refresh controller 84 for controllingthe background refresh operation in the horizontal access; a byteboundary controller 85 for controlling an access to an arbitrarycombination of bytes in the memory unit area (4-byte area) in therectangular access; and a multi-bank activating controller 83 forcontrolling accesses to a plurality of areas in the rectangular access.By performing these control operations, commands required in eachoperation, bank addresses, row addresses, column addresses, bytecombination information SB, refresh bank information SA, multi-bankinformation SA′ and the like are issued to the image memory 86.

The image memory 86 has a plurality of banks Bank 0 through 3 withinmemory core 92, and further has a row controller 87 for controllingmainly the active operation, a column controller 90 for controlling theread or write operation, and a background refresh controller 89, therecontrollers performing control with respect to the memory core 92. Therow controller 87 has a multi-bank activation controller 88, and thecolumn controller 90 has a byte boundary controller 91. A row decoderRowDec, column decoder ColDec, memory area MA, sense amplifier group SA,and input/output unit 93 for associating the memory area MA with theinput/output terminals DQ are provided in each of the banks Bank 0through 3.

FIG. 9 is a configuration diagram of the image memory according to thepresent embodiment. In the memory chip 86, the input/output terminalgroup 93 has, not only the clock CLK, but also command terminalsconstituted by RAS, CAS, WE and CS, bank address terminals BA 0 and BA1, refresh bank information terminals SA 0 and SA 1, a plurality ofaddress terminals Add, a byte combination information terminal SB with apredetermined number of bits, a data input/output terminals DQ with apredetermined number of bits, and a multi-bank information terminal SA′which is not shown.

It should be noted that the terminals SB, SA′ and SA, that are requiredin the abovementioned byte boundary function, a multi-bank accessfunction, and the background refresh function, can be realized using acommon special pin. These information items are supplied along withdifferent commands, thus input data at special pin may be set to acorresponding register in response to the supplied commands.

Also, these terminals SB, SA′ and SA can be realized using unusedterminals. For example, in the case where row addresses are inputted ataddress terminals Add 0 through 12 and column addresses are inputted atthe address terminals Add 0 through 9, the address terminals Add 10through 12 are not used when the column addresses are inputted.Therefore, control data SB, SA′ and SA can be inputted from the addressterminals Add 10 through 12 that are not used when inputting the columnaddresses.

The group of external terminals 93 are connected to internal circuitsvia buffers 94 respectively. The abovementioned group of commands isinputted to a command controller 95, and control signals correspondingto the commands are supplied to the internal circuits. Also, in responseto a mode register set command, the command controller 95 sets apredetermined set value to a mode register 96 on the basis of a set datasupplied to an address pin Add. The set information that is set by themode register 96 is supplied to the internal circuits. The rowcontroller 87 has the multi-bank activation controller 88 and a rowaddress calculator 97 required for multi-bank activation. An activepulse is supplied from the multi-bank activation controller 88 to a bankto be activated. Furthermore, a row address to be activated is suppliedfrom the row address calculator 97 to each bank. The bank Bank isprovided with a refresh row address designator 98 that designates a rowaddress to be refreshed within the bank. The refresh row addressdesignator 98 has, for example, a refresh counter for generating a rowaddress required when automatically generating a refresh command. Theinternal configuration of the bank is as explained above.

Hereinafter, image memory and memory controller are described in detailwith reference to the byte boundary function, multi-bank activefunction, background refresh function illustrated in FIG. 6 and FIG. 7sequentially.

<<Byte Boundary>>

FIG. 10 is a figure for explaining the byte boundary functions. Thisfigure shows a group of bytes (or a group of bits) selected by a rowaddress RA and a column address CA within a certain bank. As describedabove, in this example as well, 4 bytes of a data area (memory unitarea) is selected by a row address RA and a column address CA andassociated with the 32 bits of input/output terminals DQ 0 through 31.Therefore, the numbers in an intersection of the row address RA and thecolumn address CA, i.e., “0123”, indicate the bytes BY 0, BY 1, BY 2,and BY3 respectively. Also, the volume of the data area may be 4 bits,instead of 4 bytes. In this case, 4 bits of a data area (memory unitarea) is selected by a row address RA and a column address CA andassociated with 4 bits of input/output terminals DQ 0 through 3. Forsimplification, the following is an example of the 4-byte data area.

FIG. 10(A) is a conventional example in which 4 bytes of a data area isuniquely determined by a row address RA and a column address CA, and 32bits of each of 4-byte data areas (memory unit areas) 100 and 101 arealways associated with the input/output terminals DQ 0 through 31.

On the other hand, FIG. 10(B) shows the present embodiment in which a4-byte area specified by a row address RA and a column address CA isplaced in front, and any combinations of bytes are made to be associatedwith the input/output terminals DQ 0 through 31. In the figure, the4-byte area 100 selected by RA=0 and CA=0 is entirely associated withthe input/output terminals DQ 0 through 31. On the other hand, a 4-bytearea 102, which starts from the third byte after the two byte shift ofthe 4-byte area selected by RA=2 and CA=1, is associated with theinput/output terminals DQ 0 through 31. In this case, first information(start byte) for determining which byte of the 4-byte area selected byRA=2 and CA=1 to be placed in front, and second information on a byteorder (big endian or little endian) in which 4 bytes are arrangedcontinuously in an incrementing direction or decrementing direction fromthe front byte, or arranged every other byte in the incrementingdirection or decrementing direction are provided along with a readcommand or a write command.

Then, the input/output unit of the image memory extracts a total of 4bytes out of byte data corresponding to a different column address CAwithin a page, on the basis of byte combination information consistingof the first and second information, and associates the 4 bytes with theinput/output terminals DQ 0 through 31. Then, required 4-byte data isinputted/outputted once from 32 bit input/output terminals DQ.

FIG. 11 is a timing chart of the byte boundary functions. This exampleshows an example of accessing the 4-byte area 102 within the memory map12. First of all, an active command ACT (110 in the figure) is providedalong with a bank address BA=0 and a row address RA=2, the correspondingpage area is then subjected to the active operation, a read command RD(111 in the figure) is provided along with the bank address BA=0 and acolumn address CA=1 (112 in the figure), and, as byte combinationinformation 113, the first information SB=2 (114 in the figure)indicating the amount of byte shift or start byte is provided along withthe second information BMR=UP (115 in the figure) indicating thecombination pattern.

The image memory associates 2-byte data (BY 2, 3), which is the secondhalf of the 4-byte area selected by a column address CA=1, with 2-bytedata (BY 0, 1), which is the first half of the 4-byte area selected by acolumn address CA=2, in a manner shown by DQ 16-23, DQ 24-31, DQ 0-7,and DQ 8-15, on the basis of the byte combination information SB=2 andBMR=UP. This association is performed in the input/output unit 93 by thebyte boundary controller 91 shown in FIG. 9. Therefore, even in the caseof data with a different column address, 4-byte data in any combinationcan be associated with the input/output terminals DQ by providing theread command RD once. The same is true for the write command.

In FIG. 11, the same byte boundary functions can be applied, althoughthe 4-byte area selected by the row address RA and column address CA is4 bit area. In this case, 4 bit data of the 4 bit area is associatedwith the input/output terminals DQ 0 through 3.

FIG. 12 is a figure for explaining the byte boundary functions fordifferent mapping. In FIG. 12, a memory unit area to be selected by arow address RA and a column address CA is constituted by 4 bits forsimplification. The left side of FIG. 12 shows memory mapping 12-1 and12-2 showing the relationship between pixels of the image and a memoryspace, the center of FIG. 12 shows logical spaces 15-1 and 15-2 of thememory, and the right side of FIG. 12 shows a timing chart correspondingto the left and center sides of FIG. 12.

“0 through 3”, which indicate 4 bits within a 4-bit area selected by arow address RA and a column address CA, are shown within each of thememory logical spaces 15-1 and 15-2, and correspond to the input/outputterminals DQ 0 through 3 respectively. Also, “0 through 3”, whichindicate 4 bits within each memory logical space corresponding to thepixels of the image, are shown in each of the memory mappings 12-1 and12-2 on the left side. Specifically, the memory mapping shows how eachpixel of the image is associated with each of the input/output terminalsDQ 0 through 3 of the memory.

In the image system, a system designer can freely associate an imagepixel with any of the 4 bit input/output terminal DQ 0 through 3 thatare simultaneously accessed using certain addresses BA, RA and CA. Themapping 12-1 is an example of mapping four pixels arranged from left toright in the figure onto the input/output terminals DQ 0 through 3arranged in the same direction as the incrementing direction of theaddresses (from left to right), and this mapping is called “big endian”.On the other hand, the mapping 12-2 is an example of mapping four pixelsonto the input/output terminals DQ 3 through 0 arranged in the directionopposite to the incrementing direction of the addresses, and thismapping is called “little endian”.

In mapping 12-1 and mapping 12-2, the rectangular access is generated infour pixels 123 and 127 between the 6^(th) pixel to the 9^(th) pixel onthe upper left corner of the image. However, such mapping is performedin the direction opposite to that of 4 bits within the memory, thusdifferent accesses are required. Specifically, in the case of themapping 12-1, it is necessary to input/output data with respect to thepixels arranged from left to right in the image, in order of DQ1 withinCA=1, DQ2 within CA=1, DQ3 within CA=1, and DQ0 within CA=2, as shown bythe arrow 120. In the case of the mapping 12-2, on the other hand, it isnecessary to input/output data with respect to the pixels arranged fromleft to right in the image, in order of DQ2 within CA=1, DQ1 withinCA=1, DQ0 within CA=1, and DQ3 within CA=2, as shown by the arrow 124.

The bit combination information items SB, BMR are set in order torespond to such different types of mapping. Specifically, in the case ofthe mapping 12-1, as shown by 121 in the figure, a starting addressconstituted by BA=0 and CA=1 and bit combination information constitutedby SB=1 and BMR=UP are issued along with a read command RD, and, inresponse to this issuance, 3 bits of CA=1, i.e., DQ 1, 2 and 3, and DQ 0of CA=2 are simultaneously outputted as shown by 122 in the figure.

In the case of the mapping 12-2, on the other hand, as shown by 125 inthe figure, a starting address constituted by BA=0 and CA=1 and bitcombination information constituted by SB=1 and BMR=DOWN are issuedalong with a read command RD, and, in response to this issuance, 3 bitsof CA=1, i.e., DQ0, 1 and 2, and DQ 3 of CA=2 are simultaneouslyoutputted as shown by 126 in the figure.

In this manner, the bit combination information SB and BMR are specifiedin accordance with the different memory mappings such as big endian andlittle endian, whereby the image memory can input/output 4 bitssimultaneously in response to the memory mapping on the system side. Byincreasing the types of such bit combination information, a flexible 4bit access can be realized on various mapping types.

FIG. 13 is a figure for explaining the big endian and little endianshown in FIG. 12. FIG. 13 shows the image processing system at right andleft that uses a memory of which input/output bit widths consist of 4bits, wherein the left side is a big endian system that uses thedirection of the input/output terminals DQ of the memory, i.e., DQ 0through 3, as a forward direction, while the right side is a littleendian system that uses the direction of the DQ of the memory, i.e., DQ3 through DQ 0, as the forward direction.

Pixel positions (X 0 through X 11) in the screen indicate physicalpositions on the same screen. “Information on each pixel” that eachpixel position has is designated as “A” through “L” in both systems, andthis means that both systems display the same image.

In the big endian system, the pixel positions X 0 through 3 areassociated with DQ 0 through 3 of address CA 0 of the memory, the pixelpositions X 4 through 7 are associated with DQ 0 through 3 of address CA1 of the memory, and the pixel positions X 8 through 11 are associatedwith DQ 0 through 3 of address CA 2 of the memory.

In the little endian system, on the other hand, the pixel positions X 0through 3 are associated with DQ 3 through 0 of the address CA 0 of thememory, the pixel positions X 4 through 7 are associated with DQ 3through 0 of the address CA 1 of the memory, and the pixel positions X 8through 11 are associated with DQ 3 through 0 of the address CA 2 of thememory.

Specifically, when comparing the both systems, the relationship betweeneach of the pixels X 0 through 3 within the image processing system andeach of the input/output terminals T 0 through 3 in the big endian isopposite to that in the little endian. Therefore, the pixel information“A” of the pixel position X0 is stored in the physical positions (DQ 0of CA0 and DQ3 of CA0) of different memory cells in the big endiansystem and the little endian system.

Here, in the case where the image processing system generates arectangular access (130 in the figure) to pixel information “F-G-H-I” ofthe pixel positions X 5 through 8, the memory has to access the physicalpositions 132 and 134 of different memory cells in the big endian systemand the little endian system. Therefore, the minimum amount ofinformation items that are required to be supplied to the memory arethree information items, i.e., the information BMR on whether the systemis the big endian (Up) or the little endian (Down), the address CAhaving a bit as a starting point, and the positional information SB ofthe bit which is the starting point within an address.

The big endian and the little endian are the same when the memory unitarea that is accessed with the addresses RA, CA is a 4-byte area (bytegroup). FIG. 14 is a figure for explaining the byte boundary functionsin a special memory mapping. As FIG. 12, FIG. 14 shows the memorymappings 12 on the left side, the memory logical spaces 15 at thecenter, and corresponding timing charts on the right side.

In the figure, the memory mappings 12 on the left side each shows whichbit of the memory is allocated to each pixel within a frame image. Inthis example, one pixel is constituted by 2 bits of information. Forexample, an even-numbered bit holds data on luminance, while anodd-numbered bit holds data on a color difference.

Grouping-1 means a rectangular access that collects only the luminanceinformation (even-numbered bits) of pixels from the second pixel throughthe fifth pixel, and Grouping-2 means a rectangular access that collectsonly the color difference information (odd-numbered bits) of pixels fromthe second pixel to the fifth pixel on the upper left corner. In thiscase, although both Grouping-1/2 are rectangular accesses made to thesecond pixel through the fifth pixel on the upper left corner of theimage, the accesses from the image processing system to the memory andthe input/output terminals DQ that are shown in the timing charts are asfollows, due to the difference between the luminance (even-numberedbits) shown by the arrow 140 and the color difference (odd-numberedbits) shown by the arrow 144.

Grouping-1: DQ 0 of CA=1, DQ 0 of CA=2, DQ 2 of CA=0, and DQ 2 of CA=1are associated with the input/output terminals DQ 0 through 3respectively (142 in the figure), with respect to the access withCA=0/SB=2, BMR=AL (designation for collecting 4 bits every other bit)(141 in the figure).

Grouping-2: DQ 1 of CA=2, DQ 1, 3 of CA=1, and DQ 3 of CA=0 areassociated with the input/output terminals DQ 0 through 3 respectively(146 in the figure), with respect to the access with CA=0/SB=3, BMR=AL(designation for collecting 4 bits every other bit) (145 in the figure).

In this manner, the same DQs (DQ0 and DQ2 in Grouping-1, for example)are accessed simultaneously within the 4-bit area of different columnaddresses, thus the input/output units for transferring the data to theinput/output terminals DQ need to perform processing of switching theterminals for some data, i.e., processing of using a data bus of adifferent DQ.

FIG. 15 is a figure for explaining the special memory mapping shown inFIG. 14. FIG. 15 shows an image processing system that uses a memory ofwhich the input/output bit width consists of 4 bits, and particularlyshows the image processing system that uses an even-numbered DQ of thememory as the luminance information on each pixel, and an odd-numberedDQ as the color difference information on each pixel. FIG. 15(A) shows acase where only the luminance information is accessed, while FIG. 15(B)shows a case where only the color difference information is accessed.

The pixel positions (X 0 through 5) on the screen indicate the samephysical positions on the screen on both right and left. The pixelpositions hold “A, C, E, G, I, K” respectively as “luminanceinformation”, and “B, D, F, H, J, L” respectively as “color differenceinformation”.

Here, in the case where the image processing system generates arectangular access 151 to the luminance information “C-E-G-I” of thepixel positions X 1 through 4, the memory has to access only theeven-numbered DQs (153 in the figure) as shown in FIG. 15(A). In thecase where the image processing system generates a rectangular access152 to the color difference information “D-F-H-J”, the memory has toaccess only the odd-numbered DQs (154 in the figure) as shown in FIG.15(B).

The minimum information items that the memory needs to receive in orderto make such accesses are three information items, i.e., informationindicating whether the system adopts a method of holding the luminanceinformation in the even-numbered DQs and the color differenceinformation on the odd-numbered DQs (whether access needs to be madeevery other DQ) (BMR=AL), the address having a bit as a starting point(CA), and position information (SB) of the bit which is the startingpoint in the 4-bit area of the address. The column address CA and bitcombination information SB and BMR are already explained in FIG. 14.

In this case, since the same DQs (DQ0 and DQ2 in Grouping-1, forexample) are accessed with different addresses, the input/output unitfor transferring the data to the input/output terminals needs to performthe processing of switching the terminals so as to use the data bus of adifferent DQ. Therefore, a plurality of switches shown by white circlesand black circles are provided in the memory, and these switches arecontrolled based on the above-described information SB and MBR.

FIG. 16 shows timing charts showing the byte boundary functions in therectangular access. This rectangular access is an example of accessingthe rectangular area 22 shown in FIG. 6. As described above, in therectangular access, in order to read an arbitrary combination of bytedata (bit data) from an arbitrary byte position (or bit position) withina memory unit area (4-byte area or 4-bit area) selected by a columnaddress CA, the starting column address CA and, the first information SBand the second information BMR, byte combination information 166, arerequired.

FIG. 16(A) is an example in which the byte combination information itemsSB and BMR are supplied along with a read command RD. A bank addressBA=2 and a row address RA=2 are supplied with an active command ACT (161in the figure), and the first information SB=2 (164 in the figure)indicating the position of the start byte (start bit) and the secondinformation BMR=V (165 in the figure) indicating a combination of bytes(bits) are supplied along with the bank address BA=2 and the columnaddress CA=0 with a following read command RD (162 in the figure).Accordingly, the first 4 bytes (4 bits) of the rectangular area 22 shownin FIG. 6 are outputted to the input/output terminals DQ. The rest ofthree combinations of 4 bytes (4 bits) of the rectangular area 22 arealso specified by the same bank address BA, column address CA, and thebyte combination information items SB and BMR.

In FIG. 16(B), out of the bite combination information items SB and BMR,the second information BMR (165 in the figure) is suppliedsimultaneously with the mode register set command EMRS (167 in thefigure) in a register access mode before the active command ACT isissued, and this second information BMR is recorded in the moderegister. In a subsequent rectangular access, column access is madebased on this second information BMR. The active command ACT (161 in thefigure) and a read command RD (162 in the figure) in this rectangularaccess are the same as those shown in FIG. 16(A) except for the secondinformation BMR.

The abovementioned second information BMR=V can have various informationon the big endian (V=UP), little endian (V=DOWN), and the cases wherethe luminance information is stored in the even-numbered DQs and thecolor difference information is stored in the odd-numbered DQs (V=AL).

The image system can realize the byte boundary functions in therectangular access in any methods of (A) and (B) of FIG. 16.

FIG. 17 is a configuration diagram of the image processing system forrealizing the byte boundary functions. As with FIG. 8, the memorycontroller 82 for controlling the image memory 86 is provided in theimage memory 86. The address information BA, RA and CA, the bytecombination information (bit combination information) 166 that isconstituted by the first information SB indicating the start byte (startbit) within a 4-byte area (or a 4-bit area) selected by the addressinformation and the second information BMR indicating a bytecombination, and the operation commands ACT, RD and EMRS are suppliedfrom the memory controller 82 to the image memory 86.

As described above, in the timing chart (A), a read command RD or awrite command WT, which is not shown, is supplied simultaneously withthe byte combination information SB and BMR (166 in the figure). Also,in the timing chart (B), a mode register set command EMRS (167 in thefigure) is supplied simultaneously with the second information BMR, andthe read command RD or the write command WT, which is not shown, issupplied simultaneously with the first information SB.

FIG. 18 shows the byte boundary functions. This figure shows the samerectangular access as that of FIG. 6. The figures after FIG. 10 explainthe examples of a 4 bit memory unit area selected by the column addressCA. However, the rectangular access can be made by the byte boundaryfunctions also in the case where the memory unit area consists of 4bytes as described above. FIG. 18 shows such a case.

In the example shown in FIG. 18, a bank address BA, column address CA,and the byte combination information 166 constituted by the firstinformation SB and second information BMR are issued along with the readcommand RD (167 in the figure) in order to effectively access therectangular area 22 within the page area 14 (BA=0, RA=0). In response tothis issuance, 4 bytes of data items BY 0 through 3 within therectangular area 22 are outputted simultaneously to the input/outputterminals DQ. The same operation is performed in the case of a writecommand WT. Specifically, byte data items within CA1, CA1, CA0 and CA0are associated with the four 4-byte terminals BY 0 through 3 of theinput/output terminals DQ respectively in response to the first readcommand RD, and byte data items within CA5, CA5, CA4 and CA4 areassociated with the four 4-byte terminals BY 0 through 3 of theinput/output terminals DQ respectively in response to the next readcommand RD. The relationship between each column address and eachinput/output terminal in response to the rest of the read commands RD isas shown in the figure.

In this manner, the bit boundary or byte boundary functions can berealized even in the case where the width of the input/output terminalsDQ is 4 bits or 32 bits (4 bytes).

FIG. 19 is a configuration diagram of the image processing system thatrealizes simplified byte boundary functions. As described above, in thesystem designing, either one of the two memory mapping types, i.e., thebig endian and the little endian, can be selected. In theabove-described embodiment, accordingly, BMR=UP is specified for the bigendian and BMR=DOWN is specified for little endian as the secondinformation BMR of the byte combination information so that each pixelof the image can be associated with a byte position within the memoryspace even when the rectangular access is made shifting from byte tobyte.

In the example shown in FIG. 19, in the case where the system in thememory mapping 12 is designed to have a configuration corresponding tothe little endian, even if the byte boundary functions for only the bigendian can be performed to the system in the memory space 15, the entiresystem can realize the byte boundary functions for the little endian byproviding, between the image memory 86 and the memory controller 82,switching means 190 for switching the input/output terminals.

Specifically, in the case where the memory mapping on the system side isdesigned for the little endian, the switching means 190 is provided toswitch the input/output terminals 0 through 3 in the image memory 86 to3 through 0 in the memory controller 82. As a result, to the imagememory, the system side appears to respond to the big endian. Therefore,even if the system is configured to have a memory only for the secondinformation BMR=UP, the byte boundary functions for the little endiancan be realized.

FIG. 20 is a figure for explaining the image processing system thatrealizes the simplified byte boundary functions shown in FIG. 19. FIG.20(1) shows an example in which the image processing system 80 and theimage memory 86 are connected to each other via a connecting unit 200that connects input/output terminals T 0 through 3 without switchingthem. FIG. 20(2) shows an example in which the image processing system80 and the image memory 86 are connected to each other via a connectingunit 190 that switches the input/output terminals. In either case, theimage memory 86 has the bit boundary functions for only the big endian,while the image processing system 80 is a little endian type which, forassociating the 4 bit data, an input/output bit width, associates thepixel positions X 0 through 3 to the input/output terminals T 3 through0.

In FIG. 20(1), in the case where an access is made in units of addresses(A), the pixel positions (X 0 through 7) on the screen are associatedone-on-one with addresses (CA) on the memory side (X 0 through 3 andCA=0, X 4 through 7 and CA=1), thus there is no problem. However, in thecase where a signal SB is specified to make an access in units of bits(B), a shift in the pixel positions (X 1 through 4 (BCDE), 200 in thefigure) does not match with a shift in the physical positions of memorycells (CBAH, 201 in the figure) in the memory where the only bitboundary functions (BMR=UP only) corresponding to the big endian exists,thus wrong data CBAH is transferred. In this case, the BCDE on thememory cells can be outputted by means of the bit boundary functions(BMR=DOWN) corresponding to the little endian. However, if the bitboundary functions that are capable of responding to both the big endianand the little endian are provided in the memory, increase in costs iscaused.

Therefore, as shown in FIG. 20(2), the connecting unit 190 forcross-connecting the input/output terminals on the system side and thememory side is provided so that the pixels X 0 through 3 on the imagecorrespond to the DQ 0 through 3 on the memory cells, whereby the imageprocessing system 80 for little endian appears to the memory 86 to be asystem for big endian. Accordingly, the shift 200 of the pixel positionsmatches with the shift 202 of the physical positions of the memorycells, and thereby normal data BCDE can be transferred even if an accessis made while shifting bits so as to respond to the big endian.

As described above, by using the connecting unit 190 capable ofperforming cross-conversion to switch the terminals connecting thesystem and the memory, even in the case of the memory having the bitboundary (or byte boundary) functions for big endian, the bit boundary(or byte boundary) functions can be realized in the image processingsystem for little endian. Moreover, in the case of the memory having thebit boundary (byte boundary) functions for both big endian and littleendian, the memory and the system may be connected to each other via theconnecting unit 200 that makes connection without switching theterminals.

FIG. 21 is a figure showing a schematic configuration of the memoryhaving the byte boundary functions. This memory is configures a bitgroup with at least one or an arbitrary number (Nb) of bits, and hasinput/output terminals (Nb×N), which is the multiples (N), that is twoor more of the arbitrary number (Nb) of bits. A plurality of bit groups(Ng), the number of which is higher than the predetermined multiplenumber (N), configures the entire storage area (Nb×Ng). Addressinformation that can select any one of the plurality of bit groups (Ng)is received in synchronization with a first operation code. The one bitgroup that is selected by the address information is taken as a startingpoint, and the same number of bit groups as the multiple number (N) areselected in accordance with a predetermined rule. A plurality of bits(Nb×N) corresponding to the selected bit groups simultaneously deliverand receive stored information via input/output terminals (Nb×N).

The arbitrary number of bits (Nb) described above means conceptincluding both bit units and byte units, and Nb=8 (1 byte) is setaccording to the above-described embodiment. Also, the multiple number(N) explains that data items of many times of the arbitrary number ofbits (Nb) are accessed from one address, and Nb×N corresponds to thenumber of input/output terminals. N=4 is set according to theabove-described embodiment, thus the multiple number corresponds to theinput/output terminals, the number of which is equivalent to 4 bytes.More concretely, the number of input/output terminals is Nb×N, thus thenumber of input/output terminals=32 (=8×4).

Also, Ng indicating the plurality (Ng) of bit groups is the number ofgroups of all bits or bytes (groups of Nb bits) that the memory has, andis equivalent to the number obtained by dividing the capacity of theentire storage area by Nb. Normally, the number of Ng is much largerthan the multiple number (N) that is the number of bit groupsinputted/outputted at once. For example, in the case of a 64 M-bitmemory, if Nb=1, Ng=64M, and if Nb=8, Ng=8M. According to the previousexamples, when considering the 64 M-bit memory, if Nb=8, Ng=8M.According to the previous examples, the address information that canselect any one bit group is information (SB) indicating a bit which is astarting point of an address (BA, RA, CA), wherein data that is narroweddown to 4 bytes by the address (BA, RA, CA) is limited to a byte as astarting point by the information (SB) indicating a byte as a startingpoint.

Selecting the same number of bit groups as the multiple number (N) inaccordance with a rule means that, according to the previous examples, aplurality of bytes are selected in accordance with the information on acombination of bytes (BMR) that are selected simultaneously with a startbyte. Since N=4, when BMR=Up, 4 bytes that continue in the Up directioncan be accessed simultaneously from an arbitrary byte.

The image processing system accesses, via 32-bit (=Nb×N) input/outputterminals, 4 bytes that are selected by the information capable ofselecting any one bit group (1 byte according to the previous examples)(BA, RA, CA), the information on a byte that is a starting point (SB),and the information on a combination of bytes (BMR) that are accessedsimultaneously.

The amount of memory of a memory device shown in FIG. 21 is 64 bits.Therefore, eight (Ng=8) bit groups with Nb=8 bits exist. The address(BA, RA, CA) and the start byte (SB) are constituted by a total of 3bits, thus one bit group is selected from the Ng=8 bit groups. Moreover,the bit groups (N=4) that are accessed simultaneously are determined bythe combination information (BMR). Therefore, in the example shown inFIG. 21, a second group is selected by the address (BA, RA, CA) and thestart byte (SB), and four groups (group 2 through group 5) following thesecond group are accessed simultaneously from the input/output terminalsby means of the combination information BMR=UP.

If the address is incremented by one bit in the same 64 bit memory, thenumber of bit groups with a bit unit of 4 (Nb=4) is 16 (Ng=16), and ifthe input/output terminals remain Nb×N=32, the predetermined multiplenumber becomes 8 (N=8), thus seven other bit groups are selected by thecombination information BMR.

[Memory with Byte Boundary Functions]

The configuration of the image memory having the byte boundary functionsis described next in detail. According to the byte boundary functions, 4bytes of data beyond a memory unit area (4-byte area) can be selected,the memory unit area being selected by the column address. Therefore,functions for inputting/outputting 4-byte to be required data are addedto the memory. Hereinafter, for simplification, there is described anexample in which only the first information SB (referred to as “startbyte” or “start bit”) is provided as the byte combination information.The second information BMR is an example of UP only.

[Example of Internal Column Control]

First of all, several specific examples of column control performed onthe inside of the memory are described.

FIG. 22 shows a first example of the image memory having the byteboundary functions. FIG. 23 is a figure for explaining the operation inFIG. 22.

As shown in FIG. 22, the same components as the image memory shown inFIG. 9 are applied with the same reference numbers. An address signal Ais inputted by a multiple system. A row address RA is latched into a rowaddress buffer 94R, and a column address CA is latched into a columnaddress buffer 94C. The row controller 87 supplies the row address RA toa row decoder 223 of a selected memory bank 92. The column address CAwithin the column buffer 94C is also supplied to a column decoder 222 ofthe selected memory bank.

The memory bank 92 is divided into byte areas 0 through 3, which arefour memory blocks. Each byte area has a memory cell array 224, a secondamplifier 225, a pair of data latches 226 and 227, and a data bus switch228, and inputs/outputs one byte (8 bits) of data at one access. A totalof 32 bits (4 bytes) of data are inputted/outputted to an I/O bus fromthe four byte areas. The I/O bus is connected to 32 bits of input/outputterminals DQ 0 through 31 via buffers. It should be noted that FIG. 22shows only one memory bank 92, and the remaining three memory banks areomitted.

The column controller 90 has a column timing controller 220 forcontrolling the timing for operating the column decoder 222, and a datalatch selector 221 for controlling the data latch circuits 226 and 227and the data bus switch 228. The data latch selector 221 controls thedata latch circuits 226 and 227 and data bus switch 228 within each ofthe byte areas 0 through 3 in response to a column address CA and astart byte SB.

As shown in FIG. 23, suppose that 4 bytes of data from the second byteof a column address CA 0 to the first byte of a column address CA 1within a page area of a row address RA 0 are accessed. Therefore, startbyte SB=1 is established.

The memory chip 86 shown in FIG. 23 shows the relationship between thememory space and input/output terminals DQ. In FIG. 23, a 4-byte dataitem of a memory unit area that is selected by a column address CA onceis indicated by Q 00 through 15. Specifically, 4-byte data items Q 00through 03 are selected by a column address CA 0, and 4-byte data itemsQ 04 through 07 are selected by a column address CA 1.

The right side of FIG. 23 shows a timing chart. First, a bank address,which is not shown, and a row address RA 0 are provided along with anactive command ACT, so that a word line within a corresponding bank isdriven, and then a sense amplifier is activated. Thereafter, the columnaddress CA 0 and a start byte signal SB=1 as the bank combinationinformation are provided along with a read command RD. In response tothis, the column decoder 222 within the selected memory bank 92 outputsan internal decode signal 222D corresponding to the column address CA 0and an internal decode signal 222D corresponding to CA 1 obtained byincrementing CA 0 by one to four byte areas 0 through 3 in atime-sharing manner. Two 1-byte data items corresponding to CA 0 and CA1 respectively are cached to the data latch circuits 226 and 227 in eachbyte area. Then, the data bus switch 228 outputs either one of the1-byte data items, which are selected in accordance with the combinationof CA 0 and SB 1 in each byte area, from the data latch circuit 226 and227 to the I/O bus. Specifically, the data items Q 01, Q 02 and Q 03 ofCA 0 and the data item Q 04 of CA 1 are outputted to the I/O bus. Whenthe write operation is performed, the 1-byte data is inputted to eitherone of the data latch circuits from the I/O bus.

Specifically, the column decoder selects column lines (bit lines)equivalent to one byte in each byte area at one access. When the readoperation is performed, data equivalent to 1 bytes are selected from thememory cell array 224 of each byte area, are then amplified by thesecond amplifier 225 and cached to the data latch circuits 226 and 227.At this moment, memory cells that are mapped by the same column addressCA are accessed in each byte area. In order to realize a byte boundaryaccess made across the boundaries of the memory unit areas (four byteareas) that can be selected by the column address, the column decoder222 selects a column line again after ending the first access. Theaddress of this column line is CA 1, which is an address after theprevious address CA 0. 1 byte of data that is read from the memory cellarray 224 is amplified by the second amplifier, and cached to the datalatch circuit 227 different from the first access.

Therefore, 8 bytes of data items, which are twice as large as the 4-bytedata required by the input/output terminals DQ in one access, arepresent in the data latch circuits 226 and 227, thus the data bus switch228 selects 1 byte of data, i.e., half data, from 2-byte data cached tothe data latch circuits of each byte area, and transfers this data tothe I/O bus. The data latch selector 221 controls cache operation on thedata latch circuits 226 and 226 within each byte area and switchingoperation on the data bus switch 228, in response to the column addressCA0 and the start byte signal SB=1. Accordingly, byte data correspondingto different column address CA 0 and CA 1 can be transferred from eachbyte area to the I/O bus.

As a result, as shown in FIG. 23, 4-byte data items Q 04, Q 01, Q 02 andQ 03 are transferred to the input/output terminals DQ respectively viathe I/O bus. In this manner, the input/output unit 93 is configured bythe second amplifier 225, data latch circuits 226 and 227, and data busswitch 228.

FIG. 24 shows a second example of the image memory having the byteboundary functions. FIG. 25 is a figure for explaining the operationshown in FIG. 24.

The configuration shown in FIG. 24, which is different from that of FIG.22, is that, in each of the byte areas 0 through 3 within the memorybank 92, the memory cell array is divided into two arrays, 224-0 and224-1, and the second amplifier 225 and the data latch circuits 226 and227 are provided in each array. A pair of memory cell arrays 224-0 and224-1, corresponds to an even number column address CA (CA[0]=0) and toan odd number column address CA (CA[0]=1). The column decoder 222 doesnot output decode signals of CA 0 and CA 1 from the given column addressCA 0 in a time sharing manner, but outputs two decode signals 222D0 and222D1 simultaneously to the pair of memory cell arrays 224-0 and 224-1.In response to this, the pair of memory cell arrays each outputs 1-bytedata to the data latch circuits 226 and 227. Accordingly, byte areascache simultaneously 2-byte data of a provided column address CA and,the column address obtained by incrementing the column address CA byone. Then, the data latch selector 221 controls switching of the databus switch 228 in response to the column address CA and the start bytesignal SB, and transfers required 1-byte data to the input/output bus.Each of the four byte areas outputs 1-byte data, thus a total of 4 bytesof data are outputted from the input/output terminals DQ.

In the case of a write command, the 4-byte data that is supplied to theinput/output terminals DQ is stored into the two data latch circuits 226or 226 via the data bus switch 228 that is switched and controlled inresponse to the column address CA and the start byte signal SB, and thenwritten to the two memory cell arrays 224-0 or 224-1.

FIG. 25 shows an operation performed when start byte signal SB=1 andburst length BL=4. The column address CA 0 and the start byte signalSB=1 are supplied along with a read command RD, and, when the burstlength BL=4 is set by the mode register, the column decoder 222 suppliesdecode signals 222D0, 222D1 corresponding to the column addresses CA 0and CA 1 to each of the byte areas 0 through 3 simultaneously, thecolumn address CA 1 being obtained by incrementing the column address CA0 by one. In response to this, the pair of memory cell arrays 224-0 and224-1 of each byte area each outputs 1-byte data to the data latchcircuits 226 and 227 via the second amplifier 225. Accordingly, 2 bytesof data are cached from each byte area. Then, based on the column dataCA and the start byte signal SB, the data latch selector 221 supplies tothe data bus switch 228 a control signal S221 for selecting data ofeither one of the data latch circuits in each byte area (1 bit in fourbyte areas, i.e., a total of 4 bits), and then controls the switchingoperation within the data bus switch. As a result, 4 bytes of data itemsQ 04 and Q 01 through 03 are transferred to the I/O bus in the firstcycle.

In FIG. 25, since the burst length BL=4, the column decoder 222 issuesthe decode signals 222D0 and 222D1 corresponding to column addresses CA2, CA 3 in response to the control performed by the column timingcontroller 220, so as to further caches 8 bytes of data to the datalatch circuits 226 and 227. Since the data latch circuits 226 and 227need to hold 8-byte data of CA 0 and CA 1 as well, each of the datalatch circuits is configured so as to be able to hold 2 bytes of data.As a result, new 8-byte data Q 08 through 15 are latched to the datalatch circuits. Then, the data bus switch 228 transfers to theinput/output bus 4-byte data Q 05 through 08 among the 8-byte data Q 00through 07 held in the previous clock cycle and 8-byte data Q 08 through15 held in the present clock cycle. Therefore, the selected signal S221of the data latch selector 221 in this case consists of 8 bits (2 bitsin each byte area).

In the next clock cycle, the column decoder 222 issues decode signals222D0 and 222D1 corresponding to column address CA 4 and CA 5, andfurther caches 8 bytes of data Q16 through Q23 to the data latchcircuits. Then, the data bus switch 228 transfers 4 bytes of data Q 09through 12. In the next clock cycle, the data bus switch 228 transfers 4bytes of data Q 13 through 16 to the input/output bus. At this moment,it is not necessary to cache new 8-byte data from the memory cellarrays.

As with the above explanation, the write operation is performed suchthat, if the burst length BL is 4, 4 bytes of data are supplied to theinput/output terminals DQ in four cycles, and then stored in the datalatch circuits 226 and 227 via the data bus switch 228. Then, inresponse to the decode signals of the column addresses CA 0, 1, CA 2, 3,and CA 4, 5 from the column decoder 222, a total of 16 bytes of data arewritten to the memory cell arrays in three cycles.

FIG. 26 shows an operation of a modified example (1) of the secondexample of the image memory having the byte boundary functions. In theexample shown in FIG. 25, each of the byte areas 0 through 3 caches2-byte data to the pair of data latch circuits 226 and 227. However, inthe modified example shown in FIG. 26, in a first column control after aread command RD, the column decoder 222 issues the internal decodesignals 222D0 and 222D1 of the column address CA 0 and CA 1simultaneously and each byte area caches 2-byte data to the pair of datalatch circuits simultaneously. Then, in the subsequent cache operation,the column decoder 222 issues the internal decode signal 222D0 of theeven numbers (CA 2, CA 4) and the internal decode signal 222D1 of theodd number (CA 3) alternately, and each byte area caches 1-byte data tothe pair of data latch circuits 226 and 227 alternately.

Specifically, 8 bytes of data Q 00 through 07 are cached first, andthereafter 4 bytes of data Q 08 through 11, Q 12 through 15, and Q 16through 19 are cached to the data latch circuits. Then, the data busswitch 228 transfers the 4 bytes of data DQ 1 through 4, Q 05 through08, Q 09 through 12, and Q 13 through 16 to be transferred, to theinput/output bus sequentially. In this case as well, the selected signalS221 of the data latch selector 221 consists of 8 bits (2 bits in eachbyte area). As described above, in the read operation, the memory cellarrays cache the data to the data latch circuits in four cycles by meansof the decode signals of the column addresses, and the data transferoperation with respect to the input/output bus from the data latchcircuits is also performed in four cycles.

In the case of writing operation as well, 4 bytes of data are suppliedto the input/output terminals DQ in four cycles, and stored in the datalatch circuits 226 and 227 via the data bus switch 228 in four cycles.Thereafter, in response to the decode signals of the column addresses CA0/1, CA 2, CA 3 and CA 4 from the column decoder 222, a total of 16bytes of data are written to the memory cell arrays in four cycles.

FIG. 27 shows an operation of a modified example (2) of the secondexample of the image memory having the byte boundary functions. Thisexample is applied to a DDR (Double Data Rate). An SDRAM of the DDRperforms input and output of data from DQ terminals at both rising edgeand a trailing edge of a clock CLK. Specifically, 4 bytes of data Q 05through 08 are inputted/outputted at the rising edge, and 4 bytes ofdata Q 09 through 12 are inputted/outputted at the trailing edge.

Since the input/output rate is doubled in this manner, it is necessaryto double the amount of data in the memory that needs to be cached. Inthe example shown in FIG. 27, 16 bytes of data Q 00 through 03, Q 04through 07, Q08 through 11, and Q 12 through 15 are cachedsimultaneously to the data latch circuits in a first cache cycle after aread command RD, and 4 bytes out of the 16 bytes of data, i.e., Q 05through 08, are transferred to the I/O bus at the rising edge of aclock, and the next 4 bytes of data Q 09 through 12 are transferred tothe I/O bus at the trailing edge of the clock.

In order to enable such collective caching of the 16-byte data as shownin FIG. 27, the memory is divided into four memory cell arrays withineach of the byte areas 0 through 3 shown in FIG. 24, and the secondamplifier and the data latch circuits are provided in each array. Then,in each of the byte areas, the column decoder 222 provides internaldecode signals of the respective column addresses CA 0 through 3 to thefour memory cell arrays in response to the starting column address CA 1,and then 4 bytes of data are cached to four data latch circuits.Thereafter, 1-byte data of the data latch circuit selected by the databus switch 228 is transferred to the input/output bus from the four datalatch circuits by the data latch select signal S221. In the figure, acore bus corresponds to the input/output bus of the memory cell arrays,and the data of the core bus is cached to the data latch circuits.

It should be noted that the example shown in FIG. 27 is configuredwithout considering an LSB (CA[0]) of an input column address CA, andthat data items corresponding to column addresses CA 0 through 3 arealways accessed in the case of input column address CA 0 or CA 1.Specifically, column addresses to be paired are fixed regardless ofwhether the input column addresses are designated as odd numbers or evennumbers.

Moreover, in the next clock cycle, the column decoder 222 issuesinternal decode signals of column addresses CA 4 through 7 to the fourmemory cell arrays, and further caches 4 bytes of data to the four datalatch circuits. Accordingly, 16 bytes of data Q 16 through 31 arelatched to the data latch circuits, and selected 4 bytes of data out ofthe 16 bytes of data, i.e., Q 13 through 16, and 4 bytes of data Q 17through 20 are outputted at the rising edge and the trailing edge of theclock respectively.

In the write operation, write data is written in a direction opposite tothe above-described direction into the memory cell arrays from theinput/output terminals DQ via the data latch circuits.

In the case of FIG. 27 as well, the data latch select signal S221 is acontrol signal consisting of 2 bits in each byte area, i.e., a total of8 bits. Such data latch select signal is generated by the data latchselector 220 within the column controller 90 in response to a columnaddress CA and start byte signal SB.

FIG. 28 shows an operation of a modified example (3) of the secondexample of the image memory having the byte boundary functions. As withFIG. 27, FIG. 28 is an operation example corresponding to the DDR, andthe difference with FIG. 27 is that a combination of column addresses tobe accessed simultaneously in a column direction is different inaccordance with whether an input-column address CA is designated as anodd number or even number. Specifically, data items that correspond toCAs obtained by incrementing the input column address CA by one, two andthree are accessed simultaneously. In other words, in the case of aninput column address CA 1, data items of CA 1, CA 2, CA 3 and CA 4 areaccessed. Specifically, the column decoder monitors the LSB (CA[0]) ofthe input column address CA to determine column addresses to be accessedsimultaneously.

As shown in FIG. 28, the column decoder generates internal decodesignals 222D 0 through 3 of CA 1 through 4 for the input column addressCA 1, then 4 bytes of data for each byte area, i.e., a total of 16 bytesof data, are cached to the data latch circuits. Then, internal decodesignals 222D 0 through 3 of CA 5 through 8 are generated in the nextclock cycle, and 6 bytes of data are cached. Therefore, the 16-byte datato be cached are obtained by shifting 4 bytes in FIG. 27.

Therefore, the read operation and write operation shown in FIG. 28 canbe realized in the same memory configuration as the one shown in FIG.27.

FIG. 29 shows a third example of the image memory having the byteboundary functions. Also, FIG. 30 is a figure for explaining theoperation shown in FIG. 29. In the third example, 4 bytes of data Q 01through 04 to be inputted/outputted by the byte boundary functions aretransferred to/from the input/output bus by accessing each of the byteareas 0 through 3 in one column access. Specifically, unlike the firstand second examples described above, in order to access 4 bytes of datacorresponding to memory unit areas of adjacent column addresses, 8 bytesof data or 16 bytes of data are not cached from a plurality of memoryunit areas of the adjacent column addresses.

As shown in FIG. 29, the column controller 90 has a column addresscontroller 290, and supplies, to a column shifter circuit 291 withineach of the byte areas 0 through 3 within the memory bank 92, a shiftcontrol signal S290 indicating whether to shift a column address CA byone. Each byte area has the column shifter 291, the column decoder 222for decoding an output of the column shifter, the memory cell array 224for inputting/outputting 1 byte of data by means of the internal decodedsignal 222D, the second amplifier, the data latch circuit 226, and thedata bus switch 228. The column shifter 291 within each byte areaoutputs a column address to the column decoder 222 by shifting orwithout shifting the column address CA by one, in response to the shiftcontrol signal S290. The data latch circuit 226 is only required to holdonly 1 byte of data. Therefore, the data bus switch 228 always selects1-byte data within the data latch circuit 226 and transfers the data tothe I/O bus.

According to FIG. 30 showing the operation, the column addresscontroller 290 performs control so as to shift the column address CA 0by one to the column shifter 291 of the byte area 0 to generate CA 1 inresponse to the input column address CA 0 and start byte signal SB, andfurther performs control so as not to shift the column address CA 0 byone to the column shifters of other byte areas 1 through 3. As a result,in the byte area 0, 1-byte data Q 04 is accessed on the basis of theinternal decode signal 222D corresponding to the column address CA 1,and latched to the data latch circuit 226. Also, in the other byte areas1 through 3, 1-byte data Q 01, Q 02 and Q 03 are accessed respectivelyon the basis of the internal decode signal 222D corresponding to thecolumn address CA 0, and latched to the data latch circuit 226.

As described above, in the third example shown in FIG. 29 and FIG. 30,the column address has a complex configuration because the columnaddresses are generated inside the memory associated with the 4-bytedata to be accessed, but the cache operation of byte data larger thanthe 4-byte data can be eliminated. Therefore, the configuration in theinput/output unit 93 can be simplified and the power consumption withinthe memory bank can be reduced.

In the read operation, 1-byte data corresponding to a column addressprovided from the column decoder 222 in each byte area is outputted tothe data latch circuit 226, and then transferred to the input/outputterminals DQ via the data bus switch 228. In the write operation, the4-byte data that is inputted to the input/output terminals DQ is latchedto the data latch circuit 226 via the data bus switch 228 in each bytearea. Thereafter, the latched data is written to a memory correspondingto the column address from the column decoder 222 in each byte area.

In the case where the memory unit area selected by a column address isconstituted by 4 bits, the four byte areas within the bank shown inFIGS. 22 through 31 are configured as 4-bit areas, and a plurality ofcombinations or one combination of data are accessed from each bit areain a bit unit of 1.

[Control of Relationship with Input/Output Terminals]

Next, there is described an example of control of a relation between theinput/output terminals DQ within the image memory and a bus or datalatch circuit within the memory cell array.

FIG. 31 shows relation means to the input/output terminals of the imagememory having the byte boundary functions. FIG. 32 shows the operationof FIG. 31. In the relation means to the input/output terminals, asshown in FIG. 32, 4 bytes of data corresponding to a column address CAwithin the memory space are always associated with a group ofinput/output terminals DQ[7:0] through DQ[31:24], and relationshipstherebetween are not switched around dynamically. Specifically, eachrelationship (allocation relation) between the input/output terminal DQand the bus within the memory (input/output bus of the memory cell array224) is always fixed without being effected by the start byte signal SB.Therefore, even if the start byte signal SB is different at the time ofwriting and at the time of reading, the input/output terminals DQ to beinputted at the time of writing are the same as the input/outputterminals DQ to be outputted at the time of reading.

FIG. 31 shows a method of connecting the DQ terminals when accessing the4-byte data extending across a 4-byte area selected by a column addressCA. This figure assumes the read operation (SB=1) performed from Byte 1(Q01) in the 4-byte area of a column address CA 0.

In the case where the input/output terminals DQ are not switched around,data that is stored as the data of Byte 1 is outputted to the DQterminal corresponding to Byte 1, without depending on the start bytesignal SB. Therefore, connections between the memory cell array 224 andinput/output buffers 94I/O are always fixedly allocated. Therefore,designation of the start byte signal SB is performed for simplydetermining which bus of the column address CA in the memory cell array224 should be connected to the input/output butter 94I/O.

The example shown in FIG. 31 is a configuration example corresponding tothe first example shown in FIG. 22 and the second example shown in FIG.24, wherein each of the byte areas 0 through 3 is allocated to a pair ofareas (odd-numbered column address, CA[0]=0, and even-numbered columnaddress, CA[0]=1). Specifically, as with FIG. 24, there exists a memorycell area corresponding two column addresses CA, i.e., odd-numberedcolumn address and even-numbered column address, and this memory cellarea is further divided into four byte areas. The byte areas, Byte 0Area through Byte 3 Area, include the column decoder through data latchcircuits. In the case of the read operation, data that is twice as largethe data required for one-time access is outputted from the byte areas,and half of the data, i.e., 4-byte data, is connected to theinput/output buffer 94I/O at each of a group of switches (eight squaresin the figure) of the data bus switch 228.

In this manner, if the input/output terminals DQ are not switchedaround, the data Q 01 that is outputted from Byte 1 Area of the memorycell is definitely connected to the input/output terminal DQ[15:8]corresponding to Byte 1 of the input/output buffer 94I/O. Therefore, thecontrol of the data bus switch 228 using the byte start signal SB meanscontrol of connecting the input/output buffers 94I/O to either one ofthe data latch circuits of an area corresponding to the two columnaddresses CA.

The data bus switches 228 within the respective four byte areas 0through 3 shown in FIG. 24 are collectively shown as the data bus switch228 of FIG. 31. Therefore, the data bus switch 228 of each byte area isconstituted by a pair of switches corresponding to the same input/outputterminal DQ within FIG. 31.

FIG. 33 shows relation means to the input/output terminals of the imagememory having the byte boundary functions. FIG. 34 shows the operationshown in FIG. 33. In the relation means to the input/output terminals,as shown in FIG. 34, 4 bytes of data corresponding to a column addressCA within the memory space are associated sequentially with the group ofinput/output terminals DQ[7:0] through DQ[31:24], starting from thestart byte, according to the start byte signal SB, and a relationshipbetween the memory cell array 224 and each group of input/outputterminals DQ is switched around dynamically. Specifically, eachrelationship (allocation relation) between the input/output terminal DQand the bus within the memory is influenced by the start byte signal SBand thus changed. Therefore, if the start byte signal SB is different atthe time of writing and at the time of reading, the input/outputterminals DQ to be inputted at the time of writing are different fromthe input/output terminals DQ to be outputted at the time of reading.

As is clear from FIG. 34, in the case where the start byte SB=1, thedata items Q 01 through 04 within the memory are associated with theinput/output terminal groups DQ[7:0] through DQ[31:24]. Specifically,the relation between the bus or data latch circuit within the memorycell array and the input/output terminal group is configured such thatthe starting byte data is associated with the input/output terminalDQ[7:0] and the remaining 3-byte data is associated with the remaininginput/output terminals DQ sequentially according to the start bytesignal SB. Therefore, the data bus switch 228 shown in FIG. 33 isprovide with a group of input/output buses I/O bus, the buses or datalatch circuits of the memory cell array 224, and switched at allintersecting positions. The group of these switches are subjected toON/OFF control by the data latch selector 221 using the data latchselect signal S221, whereby the above-described dynamic association canbe realized.

In this manner, the input/output terminals DQ are switched around withrespect to the busses or data latch circuits within the memory cellarray according to the start byte signal SB. Specifically, the byte dataQ 01 that is outputted from the byte area Byte 1 within the memory cellarray is connected to the DQ[7:0] corresponding to Byte 0 of theinput/output buffer 94I/O when SB=“1”, and is also connected to DQ[15:8]if SB=“0”. The byte data Q05 of the byte area Byte 1 is connected toDQ[23:16] when SB=“3”, and is also connected to DQ[31:24] when SB=“2”.Specifically, the positions of the four switches in the closed state asshown in FIG. 33 are shifted to the right according to the start bytesignal SB.

Next, control of a relation between the big endian and little endian isdescribed with reference to the control of the relation with theinput/output terminals.

FIG. 35 is a configuration diagram (1) of the image memory having thebyte boundary functions and capable of corresponding to the endians. Inthis example, as with the image memory described with reference to FIG.19 and FIG. 20, the configuration within a memory core 350 correspondsto the big endian (up mode) only. Specifically, only a function ofaccessing 4 bytes of data in the up mode from byte positionscorresponding to the start byte signal SB in byte boundary operation isdescribed. Even in this case, the group of switches of the data busswitch 228 are controlled, whereby the image system for the big endianand the image system for the little endian both can realize input andoutput of proper data.

In the figure, the mode register 96 is provided with the secondinformation BMR as the byte combination information indicating the upmode or down mode, and the mode is set to either one of the modes.However, the memory core 350 having the column decoder, memory cellarray, and second amplifier that are shown in FIG. 29 and the likerespond to up mode control only. Specifically, a column control circuithas an up mode controller 351 only and does not have a down modecontroller.

FIG. 35(A) shows the data bus switch 228 for the up mode. Specifically,in the case of the up mode, which is the big endian, the memory core 350is controlled to be the up mode by the up mode controller 351.Therefore, the data bus switch 228 connects the 4 bytes of data of thedata latch circuit 226, i.e., Byte 0 through 3, to the input/outputbuffers 94I/O directly. Specifically, core data buses cdb00 z throughcdb31 z of the memory core 350 are connected directly to I/O data buspdb00 z through pdb31 z.

On the other hand, FIG. 35(B) shows the data bus switch 228 in the caseof the down mode. Specifically, in the case of the down mode, which isthe little endian, the memory core 350 is controlled to be the up modeby the up mode controller 351, but the data bus switch 228 associates 4bytes of data of the data latch circuit 226, i.e., Bytes 0, 1, 2 and 3,to 4 bytes of data of the input/output buffers 94I/O, i.e., Bytes 3, 2,1 and 0. In this case, a core bus cdbxxz and an I/O bus pdbxxz areinterchanged in units of bytes.

In the example in FIG. 35(B) showing the data bus switch 228, the samemeans as the switching means 190 of the input/output terminals shown inFIGS. 19 and 20 is provided within the image memory 86. In this manner,the memory core is configured so as to be able to respond to either thebig endian or little endian, and the above-described data bus switch 228is provided to interchange the switches thereof in accordance with thedown mode or the up mode, whereby the image memory can respond to bothendians.

FIG. 36 is a configuration diagram (2) of the image memory having thebyte boundary functions and capable of corresponding to the endians. Aswith FIG. 35, this image memory has a memory core configuration capableof corresponding to the up mode control only, and the data bus switch228 is switched in accordance with the second information BMR=UP/DOWNthat is set in the mode register 96, whereby the image memory canrespond to both modes. The difference with FIG. 35 is that switching ofdata performed by the data bus switch 228 is carried out so that MSB (DQ31) and LSB (DQ 00) are interchanged. Specifically, in addition to 4bytes, 8 bits of data in each byte are also changed.

FIG. 37 is a configuration diagram (3) of the image memory having thebyte boundary functions and capable of corresponding to the endians.This image memory corresponds to the image memory shown in FIG. 29,wherein a combination of column addresses of respective four byte areaswithin the respective memory cores 350 is controlled to be changed inresponse to the operation mode, and 4 bytes of data extending in the updirection or down direction from the byte corresponding to the startbyte signal SB are inputted/outputted from the four memory arrays.

For example, when the column address CA 0 and start byte SB=1 as shownin FIG. 30, the internal column addresses of the four byte areas Byte 0through 3 become CA 1, CA 0, CA 0 and CA 0 respectively in the case ofthe up mode, and data items Q 04, Q 01, Q 02 and Q 03 areinputted/outputted from 4 bytes of input/output terminals DQ. In thecase of the down mode, on the other hand, the column addresses become CA0, CA 0, CA 1 and CA 1 respectively, and data items Q 00, Q 01, Q 06 andQ 07 are inputted/outputted from 4 bytes of input/output terminals DQ.

In this manner, the column address to be provided to the four byte areasByte 0 through 3 within the respective memory cores are switched aroundby the column shifter 291 in accordance with the up mode or down mode.Then, a combination of column addresses, which is uniquely determined bythe start byte signal SB and the mode signal BMR, is supplied to eachbyte area of each memory core 350 via the column shifter 291. Thiscolumn shifter 291 selects one of the two column addresses required tobe switched around, in accordance with the up mode/down mode Up/Down,the two column addresses being selected from four column addresses caby0z through caby3 z from a column address controller 90A. Specifically, inthe byte area Byte 0, either cabyoz or caby3 z is selected. In the bytearea Byte 1, either caby1 z or caby2 z is selected. In the byte areaByte 2, either caby1 z or caby2 z is selected. Also, in the byte areaByte 3, either caby0 z or caby3 z is selected.

In the case of a single data rate (SDR), 4 bytes of data is only able tobe accessed at one access, thus, as described with reference to FIG. 29,1-byte data that is held in the data latch circuit corresponding to eachbyte area may be transferred directly to the input/output bus.

In the case of a double data rate (DDR), on the other hand, 4 bytes of8-byte data need to be inputted/outputted at one access. Therefore, inthe configuration shown in FIG. 29, each of the byte areas Byte 0through 3 is provided with a block of even column addresses (CA[0]=0)and a block of odd column addresses (CA[0]=1), then a combination ofcolumn address, which is uniquely determined by the start byte signal SBand the mode signal BMR, is supplied from the column shifter 291 to thepair of blocks, and required 4 bytes of data are selected by the databus switch 228 and transferred to the input/output bus I/O bus. In thiscase, each switch within the data bus switch 228 selects the data of theeven block or odd block in response to control signals dabyaz throughdabydz sent from the data latch selector 221, and transfers the selecteddata to the input/output bus I/O bus. For this reason, column addressesdaby0 z through daby3 z for the data bus are supplied from a columnaddress controller 90B to the data latch selector 221, and the datalatch selector 221 selects, or the four byte areas, one of two byterequired to be switched in accordance with the up mode/down modeUp/Down. The combination of candidates for switching is same as thecolumn shifter 291 described above.

As shown in FIG. 37, by controlling the combination of column addresses,the number of switches within the data bus switch 228 can be reduced.Specifically, in the data bus switch shown in FIGS. 35 and 36, 2N*8switches are required when the number of input/output terminals DQ is Nbytes. However, by controlling the combination of column addresses, asshown in FIG. 37, 2N number of switches are required in the columnshifter 291 and in the data bus switch 228, respectively thus a total of4N number of switches are required. Therefore, the number of switchescan be reduced to ¼ from the number of switches shown in FIGS. 35 and36.

FIG. 38 is an operation timing chart of the up mode of the DDR memoryshown in FIG. 37. In this example, the column address is CA1 and thestart byte signal SB is 1, and the data items DQ 05 through 08 stored inthe memory 86 in the big endian are read out. Specifically, therelationships between the data items Q 00 through 19 and theinput/output terminals DQ corresponding to the column addresses withinthe memory 86 are as shown in the figure.

As described above, in the case of the DDR memory, each byte area withinthe memory cell array has the block of even column addresses (CA[0]=0)and a block of odd column addresses (CA[0]=1), then a controlledcombination of column addresses caby is supplied to these blocks, and acontrolled combination of column addresses for switching the data buses,daby, is supplied to the data bus switch 228.

Specifically, CA 1 is inputted as a base column address CA. Along withthis input, the column addresses CA that are supplied to the even block(CA[0]=“0”) and odd block (CA[0]=“1”) within each of the byte areas Byte0 through 3 are controlled. A column line of the column address CA 2 isactivated in the area of the even block (CA[0]=“0”). A column line ofthe column address CA 3 is activated in the byte area Byte 0, and columnlines of the column addresses CA 1 are activated in the byte areas Bytes1, 2 and 3 in the area of the odd block (CA[0]=“1”).

As a result, the data items Q 05 through 12 are outputted to the corebuses of the memory cores. Specifically, the data items Q 08 through 11are outputted to the core buses of the even block, and the data items Q5 through 7 and also Q 12 are outputted to the core buses of the oddblock.

In the DDR memory, it is necessary to transfer 4 bytes of data from this8-byte data to the I/O bus. Here, on the basis of the start byte signalSB and the column address CA, the data bus switch selects the data ofthe even block (CA[0]=“0”) in the byte area Byte 0 only. As a result,the data items Q 05 through 08 can be outputted to the input/outputterminals DQ.

Here, in each of even block area and odd block area (CA[0]=“0”/“1”), theinternal column address cabyaz selects caby0 z, an internal columnaddress cabybz selects caby1 z, cabycz selects caby2 z, and cabydzselects caby3 z. Similarly, in each of even block area and odd blockarea (CA[0]=“0”/“1”), the column address for data bus, dabyaz, selectsdaby0 z. Similarly, dabybz selects daby1 z, dabycz selects daby2 z, anddabydz selects daby3 z.

FIG. 39 is an operation timing chart of the down mode of the DDR memoryshown in FIG. 37. In this example, the column address is CA1 and thestart byte signal SB is 2, and the data items DQ 05 through 08 stored inthe memory 86 in the little endian are read out. Specifically, therelationships between the data items Q 00 through 19 and theinput/output terminals DQ corresponding to the column addresses withinthe memory 86 are as shown in the figure. The difference with FIG. 38 isthat the relationships between 4 bytes of data and the input/outputterminals DQ are opposite to those shown in FIG. 38.

In this case, CA 1 is inputted as the base column address CA. Along withthis input, the column addresses CA that are supplied to the even block(CA[0]=“0”) and odd block (CA[0]=“1”) within each of the byte areas Byte0 through 3 are controlled. A column line of the column address CA 2 isactivated in the even block (CA[0]=“0”). A column line of the columnaddress CA 3 is activated in the byte area Byte 3, and column lines ofthe column addresses CA 1 are activated in the byte areas Bytes 2, 1 and0 in the odd block (CA[0]=“1”).

As a result, the data items Q 05 through 12 are outputted to the corebuses of the memory cores. Specifically, the data items Q 08 through 11are outputted to the core buses of the even block, and the data items Q5 through 7 and also Q 12 are outputted to the core buses of the oddblock.

In the DDR memory, it is necessary to transfer 4 bytes of data from this8-byte data to the I/O bus. Here, on the basis of the start byte signalSB and the column address CA, the data bus switch selects the data Q 08of the even block (CA[0]=“0”) in the byte area Byte 3 only, and selectsthe data items Q 05 through 07 from the odd block for the rest of thebyte areas. Accordingly, 4 bytes of data items Q 05 through 08 can beoutputted to the input/output terminals DQ.

Here, in each of even block area and odd block area (CA[0]=“0”/“1”), theinternal column address cabyaz selects caby3 z, an internal columnaddress cabybz selects caby2 z, cabycz selects caby1 z, and cabydzselects cabyoz. Similarly, in each of even block area and odd block area(CA[0]=“0”/“1”), the column address for data bus, dabyaz selects daby3z. Similarly, dabybz selects daby2 z, dabycz selects daby1 z, and dabydzselects daby0 z.

As described above, when comparing the down mode shown in FIG. 39 withthe up mode shown in FIG. 38, cabyz and dabyz are switched between thebyte areas Byte 0 and Byte 3 and between the byte areas Byte 1 and Byte2, whereby the mode can correspond to the arrangement of byte data itemsin two types of endians, the big endian and little endian. FIG. 40 is afigure for explaining a method of designating a boundary of the byteboundary functions. In the figure, in the byte boundary function wherean access is made across the boundaries of adjacent four byte areas ofthe column address CA[7:0]=#n and #n+1, a case in which the boundarydesignation method is performed based on the start byte SB and a casewhere the boundary designation method is performed based on a shiftvalue SV are considered. The start byte SB=N means that an access ismade across 4 bytes from a byte N, and the shift value SV=N means thatan access is made across 4 bytes from a position shifted by N bytes froma border of 4-byte areas of column address.

In this case, the relationship between the start byte SB and the shiftvalue SV changes in the up mode and the down mode in accordance with thetwo modes of the endian. Specifically, in the case of the up mode, sincethe byte data items are arranged in the manner of Byte 0 through 3, SBand SV are the same. However, in the case of the down mode, the bytedata items are arranged in the manner of Byte 3 through 0, thus SB andSV are different and in an opposite relationship.

Therefore, in the case where the image memory has a start byte signal SBterminal only and the internal structure is controlled in accordancewith the shift value SV, it is necessary to non-invert or invert thestart byte signal SB so as to obtain the shift value SV depending onwhether the mode is the up mode or down mode. The same is true for thecase where the image memory has a shift value SV terminal only and theinternal structure is controlled in accordance with the start byte SB.

FIG. 41 shows a conversion circuit of the start byte SB and the shiftvalue SV. A conversion circuit 410 consists of 2 bits 410[0], 410 [1],and is constituted by CMOS transfer gates 412 and 413, and inverters 414and 415. An input start byte SB is non-inverted or inverted so as toobtain the shift value SV according to a count-type signal indicatingthe up mode or the down mode. As shown in a truth table 411 of theconversion circuit 410, the SB is not inverted to becomes SV in the caseof the up mode, but SB is inverted to becomes SV in the case of the downmode.

[Column Address Control in Rectangular Access]

As shown in FIG. 1, in the memory mapping 12 and 14E for associating thememory space of the image memory with the pixels of the image, withinthe page area 14 selected by a bank address BA and a row address RA, themapping is performed so as to wrap a memory unit area (4-byte area)selected by the column address CA at a predetermined wrap width (CAWrap), in accordance with the arrangement of the matrix of pixels in theimage. In the example shown in FIG. 1, the column address CA is wrappedin units of 4 within the page area 14. That is, the wrap width CA Wrapof the column address is 4. This wrap width of the column address isalso called “step” of the column address.

By this mapping of wrapping the memory unit area selected by the columnaddress at a predetermined wrap width, efficiency of a rectangularaccess that is made frequently in the image memory can be improved.Specifically, while a page area is subjected to active operation by anactive command, a read command and a write command are repeatedly issuedin accordance with a rectangular area to be accessed, whereby an accesscan be made to the rectangular area within the same page area. Since anaccess can be made to the rectangular area within the same page area byperforming the active operation once, an efficient access can be made.

As shown in FIG. 16, in such rectangular access, it is necessary torepeatedly issue the read command RD, bank address BA, column addressCA, and start byte signal SB. However, if the mapping information of thememory, or particularly the wrap width (CA Wrap) of the column addressCA of the page area is already known, the starting column address CA ofthe rectangular area, rectangular width and the rectangle size can beprovided so that the image memory can internally and automatically issuethe column address to be accessed, whereby the image data of therectangular area can be accessed. In this case, the read command and thecolumn address may be issued once, thus it is not necessary to issuethem a number of times as in FIG. 16.

FIG. 42 is a figure for explaining an automatic rectangular access usingthe byte boundary functions. In this example, data areas to be accessedare shown by arrows in a memory mapping 421. In this memory mapping,column addresses CA are wrapped at 8 within a page area 14. Thus, thecolumn address wrap width CAWrap is 8. Therefore, column addresses CA ona right end of the page area 14 are #07, #0F, #17 and #1F (Hexadecimal),and the wrap width CAWrap is 8. Also, the starting address CA of therectangular area to be accessed is CA=#B, the start byte SB=2, the widthof the rectangular area Rwidth=2 clocks (4 bytes×2 clocks=8 bytes), andthe size of the rectangular area is burst length BL=8 (4×8=32).Therefore, the height of the rectangular area is BL/Rwidth=4.

FIG. 43 is a timing chart of an automatic rectangular access. FIG. 44 isa configuration diagram of an internal column address calculator that isrequired in the automatic rectangular access. In order to perform therectangular access shown in FIG. 42, column addresses CA=#0B/#0C,#0C/#0D, #13/#14, #14/#15, #1B/#1C, #1C/#1D, #23/#24, and #24/#25 may beissued within the memory in response to supplied column addresses CA=#0Band SB=2. Specifically, in the first access, Bytes 2 and 3 access toCA=#0B, and Bytes 0 and 1 access to CA=#0C. In the second access,progress is made in the column address CA by 1, thus Bytes 2 and 3access to CA=#0C, and Bytes 0 and 1 access to CA=#0D. In this example,since the rectangular width RWidth=2, the third access is made towrapped column addresses CA=#13 and #14 in place of the position afterthe column address CA is shifted by 1. Therefore, it is necessary tocompute the third column address from the column address wrap widthCAWrap and the rectangular width Rwidth. When considering this thirdaddress with Bytes 2 and 3, third CA to be accessed is obtained asCA=12+8−2+1=19 (Decimal)=#13 (Hexadecimal) by an equation shown in FIG.43 (CA+CAWrap−Rwidth+1) on the basis of the current column addressCA=#0C (=12 (Decimal)), CAWrap=8, and RWidth=2. FIG. 44 shows the columnaddress calculator within the column controller 90. This calculator hasa column address counter 440 that increments by one a column address CAsupplied from the outside and a wrapped column address CA (Wrap), insynchronization with an internal clock pclenz that synchronizes with thetiming of a clock, a computer 441 that adds CA Rwap to a count value ofthe column address counter and subtracts Rwidth, a switch 442 forselecting an output of the computer 441 when the rectangular area iswrapped, a rectangular width counter 444 that counts the synchronizingclock pclenz and counts count values in the horizontal direction duringan access, and a comparator 445 that detects that the horizontal countvalue widthz of the rectangular width counter 444 matches with therectangular width Rwidth, and generates a switching signal wrapz for theswitch 442.

Explanation is provided with reference to the timing chart shown in FIG.43. First, suppose that the rectangular area size is set as burst lengthBL=8 in the mode register, and the wrap width of a column addressCAWrap=8 within a page area is also set in the mode register. Then, thestarting column address CA=#0B, start byte SB=2, and rectangular widthof the rectangular area to be accessed Rwidth=2 are supplied along witha read command 430 following an active command. In response to this, thetiming clock pclenz is generated in synchronization with a clock, therectangular width counter 444 then counts up the count values widthz inthe horizontal direction during the access, and the column addresscounter 440 counts up starting from the starting column address CA=#0B.

An internal column address caz[7:0] that is issued for the first accessis CA=#0B/#0C, as shown in FIG. 43. In the second access, #0C/#0D isoutputted in response to the column address caz[7:0]=#0C obtained byincrementing caz=#B by one by the column address counter 440. In thethird access, the rectangular area needs to be wrapped at a rectangularwidth, thus a computed value of the computer 441 is selected by theswitch 442, column address caz[7:0]=#03 is outputted, and, afterwrapping is performed in response to this output, column addressCA=#13/#14 is generated. In the fourth access, #14/#15 is generated. Inthe fifth access the rectangular area is wrapped and #1B/#1C isgenerated. Thereafter, #1C/#1D, #23/#24 and #24/#25 are generatedsimilarly.

The configuration of the image memory corresponding to this automaticrectangular access is as shown in, for example, FIG. 29, wherein acombination of four column addresses corresponding to the byte boundaryfunctions is supplied to four byte areas Bytes 0 through 3.Specifically, a combination of the internal column addresses caz shownin FIG. 43 is supplied to the column decoder in each byte area. As aresult, the data items of these column addresses are outputted from thefour byte areas respectively.

In the above example, the rectangular width Rwidth at the time ofrectangular access is supplied along with the read command, but therectangular width Rwidth may be set beforehand by means of the moderegister set command in the mode register. Alternatively, the rectanglesize BL and rectangular width Rwidth may be supplied along with the readcommand. The wrap width CAWrap of the column address is set by the imagesystem beforehand, thus it is preferred that the wrap width CAWrap isset by means of the mode register set command.

In this manner, in the case of the rectangular access, if the columnaddress CA as a starting point, the rectangular width Rwidth, and therectangle size (BL) are provided, an internal column address to beaccessed can be generated automatically on the basis of the wrap widthCAWrap of the column address that is set beforehand. Therefore, therectangular access can be made by issuing a read command once.

[Byte Boundary Functions of Page Area Boundary]

The byte boundary functions can efficiently access predetermined bytes(4 bytes) of data across the boundary of a memory unit area (4-bytearea) selected by a column address. However, in the case of performing arectangular access across a page area boundary, adjacent page areas needto be subjected to the active operation again by means of another activecommand.

FIG. 45 shows an example of memory operation performed when an accessmade by the byte boundary functions reaches the end of a page area. Thisfigure shows an example in which the page area is constituted by columnaddress CA[7:0]=#00 through #FF and CA=#FF at a right end. In this case,when 4 bytes of data items shown by arrows in the figure are accessedusing the byte boundary functions, the 4 bytes of data can be outputtedin the up mode when SB=0, but when SB=1, 2 and 3 the byte data at a leftend are accessed after turning at the right end of the page area.Specifically, in this example, the access is performed again within thesame page area without performing new active operation. In the case ofthe down mode, on the other hand, it is necessary to turn at the leftend to move to the right end (Wrap) when SB=0, 1 and 2, turning does notneed to be performed only when SB=3.

If the abovementioned access is made, unnecessary data is outputted. Inorder to make an access to an adjacent page area from the end of theabove page area, it is necessary to issue a new active command toperform active operation on the adjacent page area.

FIG. 46 shows another example of the memory operation performed when anaccess made by the byte boundary functions reaches the end of a pagearea. In this example, the burst length BL is set to 8. When BL=8 isestablished, a burst counter within each bank repeatedly counts internalcolumn addresses by means of the counter width of BL=8. Specifically, inthe example shown in FIG. 46, the internal column addresses that aregenerated by the burst counter are constituted by a width 8 of CA=#k8through #kF (16-bit notation). Even in the case of a memory in which theaccess area is divided by such counter into rectangular areas that usethe burst length BL as the base, when, as with FIG. 45, the byteboundary functions are used at the right end where the burst length areaCA=#k8 through #kF, the same problem as FIG. 45 is generated. In theexample shown in FIG. 46, wrapping occurs at SB=1, 2 and 3 at the timeof the up mode, and wrapping occurs at SB=0, 1 and 2 at the time of thedown mode. Accordingly, unnecessary data is outputted.

FIG. 47 shows yet another example of the memory operation performed whenan access made by the byte boundary functions reaches the end of a pagearea. In this example, the byte boundary functions are realized usingthe multi-bank access function in the rectangular access described withreference to FIG. 7. Specifically, the row address RA=#n is specified bythe active command ACT. If the column address CA as the base point isCA=#FF at the right end of the page area when the read command RD isissued, an access is made beyond a boundary PB of the page area as shownby the arrows.

Specifically, in the up mode, when SB=1, 2 and 3, an access is made tothe byte data of CA=#FF within the page area where RA=#n and to the bytedata of CA=#00 within the page area where RA=#n+1. In the down mode,when SB=0, 1 and 2, an access is made to the byte data of CA=#FF withinthe page area where RA=#n and to the byte data of CA=#00 within the pagearea where RA#n+1. In this case, an access needs to be made to adjacentpage areas, thus the page area with the row address RA=#n that isprovided along with the active command ACT is activated, and, inresponse to the column address CA=#FF and start byte signal SB=2 thatare supplied along with the read command RD, the page area with theadjacent row address RA=#n+1 is activated. Thus, word lines within aplurality of banks are activated in response to one active command ACT.

When control is performed such that the plurality of banks are activatedsimultaneously, data of required areas can be inputted/outputtedeconomically, even if the byte boundary functions are requested at theend of the page area.

[Other Application of Byte Boundary Functions]

The byte boundary functions can input/output data efficiently whenstoring the image data to the memory and accessing the datacorresponding to an arbitrary pixel. The byte boundary functions havethe same benefits in an application other than the image memory.

FIG. 48 through FIG. 50 are figures for explaining other application ofthe byte boundary functions. FIGS. 48 and 49 correspond to aconventional example, and FIG. 50 corresponds to the present embodiment.According to the configuration of the memory, a plurality of byte areasare allocated to the same column address CA, and an access is made to aplurality of byte data items that are allocated to the same columnaddress CA at one access. In such structure, the memory can be accessedefficiently when processing data of fixed byte size (word configuration)allocated to the same column address CA.

However, there is a case where the size of data to be processed by thesystem is less than that of the word configuration of the memory. As acountermeasure for such a case, there is a method padding so that thedata of the word configuration size or smaller does not extend across aplurality of column address CA areas. In the example shown in FIG. 48,the word configuration of the memory is set to 4 bytes (see 483 in thefigure), and the units of the size of the data to be processed may be 1byte (format A of 280 in the figure), 2 bytes (format B of same), or 4bytes (format C of same). Therefore, the data of 4 bytes is preventedfrom extending across the column addresses CA by storing the data in theposition where Byte 0 is the base point. The data of 2 bytes is storedin the positions where Byte 0 and Byte 2 are the base points. The dataof 1 byte can be stored in the positions where any of Byte 0, Byte 1,Byte 2 and Byte 3 is the base point.

Suppose that there is a case where data 0 through 5 of the sizes, 2Byte, 4 Byte, 1 Byte, 2 Byte, 2 Byte and 1 Byte, are continuously storedin the memory, as with the write data 482 shown in the figure. In thiscase, by performing the write operation as in 481 in the figure, paddingis performed in several byte areas within the memory as shown in 483 inthe figure, and a total of 4 bytes of areas are not used effectively forstoring the data. In this case, the amount of memory is not usedeffectively. However, by outputting data in a unit of 4 bytes by thecolumn address CA, each data item can be read at one column addressaccess, thus reading speed increases.

However, in order to eliminate the above mentioned redundant storagecapacity, the data items may be stored continuously in to the byte areasof the memory without performing padding. For example, the data iswritten in three cycles by means of a write command WR as shown in 491in FIG. 49, and then the data can be stored in the byte areas within thememory as shown in 493 in the figure.

By writing the data in the manner shown in FIG. 49, the storage capacityof the memory can be utilized effectively. However, in the case wherethe data is stored across different column address areas, such as 2-bytedata items B03 and B13 in data 3 or 4-byte data items C 01 through 31 indata 1, reading and writing cannot be performed at one access in aconventional memory, thus access needs to be made twice. As shown in 491in the figure, the read command RD needs to be issued twice to read data4, deteriorating the access efficiency.

Therefore, as shown in 500 in FIG. 50, by issuing the read command RDonce and specifying the start byte signal SB=3 by means of the byteboundary functions, data 3 (B03 and B 13) extending across the differentcolumn addresses can be accessed. Therefore, the memory having the byteboundary functions can realize the improvement of the memoryavailability without reducing the access performance.

[Memory Controller for Byte Boundary Functions]

Next, the memory controller for the byte boundary functions isdescribed. The image processing system is described with reference toFIG. 8, wherein the image processing controller 81 and the memorycontrolling section (memory controller) 82 are included in the imageprocessing chip 80 within the image processing system.

FIG. 51 is a configuration diagram of the image processing system. Aswith FIG. 8, the image processing system is constituted by the imageprocessing controller 81, memory controller 82, and image memory 86. Theimage processing controller 81 is configured so as to perform, forexample, MPEG decoding processing. The image processing-section 81 hasan entropy decoding processor 510 to which a coded and compressed streamdata S™ is inputted, an inverse quantization and inverse IDC processor511 for performing data processing on the basis of a DCT coefficientDCT-F, an intra prediction section 512, an inter prediction section 513for having the memory controller 82 read a reference image on the basisof a motion vector MV and a micro-block division information MBdiv, anda process selecting section 515. The memory controller 82 performsmemory control including issuance of commands and addresses between theimage processing controller 81 and the image memory 86. Decoded imagedata D-IMG that is outputted from the process selecting section 515 isstored into the image memory 86 by the memory controller 82. Also, the areference image read controller 514 of the inter prediction section 513acquires data of a reference image R-IMG from the image memory 86 viathe memory controller 82, and sends the data of the reference image tothe process selecting section 515.

An MPEG decoder decodes current image data on the basis of the referenceimage R-IMG within a past image or future image that is read from thememory on the basis of the motion vector, and on the basis ofdifferential data between the reference image and the current imagedata. Therefore, an operation is frequently performed in which arectangular reference image located in the position of the motion vectoris read out from the image that is temporarily stored in the imagememory 86. In this rectangular access control, the access efficiency canbe improved by using the image memory 86 having the byte boundaryfunctions and the memory controller 82 corresponding to the byteboundary functions.

FIG. 52 shows input and output signals of the memory controlling section(memory controller). FIG. 53 is a figure for explaining a referenceimage area, which is a target of reading within a frame image. In aframe image FM-IMG, the upper left indicates the origin (0, 0) of apixel coordinate. In order to specify an area for the rectangularreference image RIMG, a coordinate (POSX, POSY) at the upper left of therectangle and the size in length and width, i.e., SIZEY and SIZEX, arerequired. Therefore, the reference image reading controller 514 withinthe image processing section supplies the above information items (POSX,POSY), SIZEY and SIZEX specifying the area of the reference image RIMG,to the memory controller 82. Moreover, a direct memory access controlsignal DMA-CON is inputted/outputted between the reference image readingcontroller 514 and the memory controller 82.

On the other hand, the memory controller 82 computes addresses Addwithin the memory space (bank address, row address, column address) onthe basis of the information items (POSX, POSY), SIZEY and SIZEXspecifying the reference image area, and supplies the command CMD,addresses Add, multi-bank access information SA′, start byte signal SB,write data Data and the like to the memory 86. Also, the memorycontroller 82 receives the read data Data read from the memory 86.

FIG. 54 is a detailed configuration diagram of the memory controller.The memory controller 82 has interface controllers 541-1 through N thatreceive the information items POSX, POSY, SIZEX and SIZEY for an imagearea to be accessed, and the write data Data from access request sourceblocks 81-1 through 81-N that requests an access to the memory as in theabovementioned image processing controller, and address/commandgenerating sections 542-1 through N that receive the abovementionedreference image information items via these interface sections andgenerate addresses and commands. These interface controllers and theaddress/command generating sections should be activated or arbitrated byan arbitration circuit 540. The address/command generating sections 542that are selected and activated by the arbitration circuit 540 issue thecommand CMD, addresses Add (bank address, row address, column address),multi-bank access information SA′, start byte signal SB and the like tothe memory 86 via a selector SEL. Accordingly, for the access requestsource blocks that are selected by the arbitration, the memorycontroller 82 controls an access made to the memory 86 and writes orreads the data. Also, the memory controller 82 makes a refresh requestto the memory with required frequency.

The command CMD issued by the memory controller 82 includes, forexample, the mode register set command, active command, read command,write command, precharge command, refresh command, and other commandsrequired in normal SDRAM. Furthermore, in a setting register 543 withinthe memory controller 82, the address of an upper-left pixel of theframe image FM-IMG, the memory mapping information, and information onthe functions provided in the memory 86 are set. The functions providedin the memory are the multi-bank access function, the function ofswitching around the arrangements of the data corresponding to theendians, and other functions. The presence of the functions provided inthe memory, the target of control, is set in the setting register 543.

FIG. 55 is a figure for explaining computation performed by the interprediction section 513 in the reference image reading controller 514. Inthe case of an MPEG image, macroblock MB is the unit for processing. Themacroblock MB is constituted by luminance data of 16×16 pixels, and acolor difference (Cb, Cr) data of 8×8 pixels (Y:U:V=4:2:0). ¼ macroblockQMB, which includes luminance data of 8×8 pixels obtained by dividingthe macroblock MB into four, is the unit for processing the motionvector MV and the reference image RIMG. When an upper-left coordinate ofthe macroblock MB, that is being processed currently, is (MBaddrx,MBaddry) macroblock division information thereof is Mbdivx, Mbdivy andthe motion vector is MV=(MVx, MVy), a computation processor 515 uses ancomputing equation shown in the figure to obtain the upper-leftcoordinate (POSX, POSY), width SIZEX, and height SIZEY of the referenceimage RIMG. This width SIZEX is set as a multiple number of the numberof bytes inputted/outputted at one access to the memory, and the heightSIZEY is set as the number of pixels in the vertical direction.

The reference image specifying information (POSX, POSY), SIZEY, andSIZEX that are computed in the manner described above are outputted fromthe reference image controller 514 to the memory controller 82, and, onthe basis of the reference image specifying information, memory mappinginformation, and upper-left addresses in the frame area that are set inthe setting register 543, the command/address generating sections 542within the memory controller 82 generates an address of the memory spacerequired in rectangular access.

FIG. 56 shows an example of computation performed by the interprediction section 513 in the reference image reading controller 514.This is a specific example of FIG. 55. First, the upper-left coordinateof the macroblock MB is (MBaddrx, MBaddry)=(0 and 0), macroblockdivision information is Mbdivx, Mbdivy=8, and motion vector MV=(MVx,Mvy)=(13 and 4), thus the upper-left coordinate of the reference imageRIMG (POSX, POSY), width SIZEX, and height SIZEY are obtained in thefollowing computation:

POSX=0+8+13=21

POSY=0+8+4=12

SIZEX=8,SIZEY=8

The rectangular area of the reference image RIMG does not conform to theunit of a 4-byte area selected by a column address. In order to conformthe rectangular area to the unit of the 4-byte area, an access needs tobe made to the area with the upper-left coordinate (20 and 12), width 12and height 8, such as an enlarged area E-RIMG in FIG. 56. However, byusing the byte boundary functions, an access with byte unit can be madeacross the boundary of the 4-byte unit. In this manner, when making anaccess to reference image data such as an MPEG image, the byte boundaryfunctions contribute to improving the access efficiency.

FIG. 57 shows an example of memory mapping. As with the memory mapping12 shown in FIG. 1, a pixel of the image and the page area 14 within thememory space are associated with each other as in the memory mapping 12,and adjacent page areas are disposed so as to have different bankaddresses BA. The page area 14 is an area selected by a bank address BAand a row address RA, and each page area 14 is constituted by aplurality of memory unit areas (4-byte areas) selected by columnaddresses respectively. In the example shown in FIG. 57, each page area14 is a unit for storing image data of 64 pixels×16 pixels.

FIG. 58 shows the configuration of the page area 14 in the memorymapping 12. The page area 14 that is specified by a row address RA 0within a bank BANK0 has memory unit areas indicated by column addressesCA 0 through 255. 4 bytes are selected by each column address, and awrap width (step width) of each column address CA is 16. Therefore, thepage area 14 has a width of 64 (=4×16) bytes and a height of 16(=256/16) bytes.

FIG. 59 shows an arrangement of the reference image area being shown inFIG. 56 on the memory map. As shown in FIG. 59, the reference image areaRIMG has the upper-left coordinate (21 and 12), a width of 8 and aheight of 8, and thus corresponds to a memory area with a width of 8bytes and a height of 8 bytes, the memory area being formed startingfrom a byte BY 1 in a leading address of a column address CA 5.Specifically, a left end 591 in a rectangular access area is shifted by1 byte (592 in the figure) from a boundary 590 obtained from a columnaddress CA. Therefore, a bank address BA 0 and a row address RA 0 isissued along with the active command ACT to the memory having theabove-described byte boundary functions, and the starting column addressCA 5, CA 6 through 117, and CA 118 and the start byte signal SB=1 iscontinuously issued along with the read command RD (or write commandWR). Also, for the memory having the automatic internal column addressgenerating functions shown in FIGS. 42 through 44, the column addresswrap width CAWrap=16 is set, and the starting column address CA 5, startbyte signal SB=1, rectangular width Rwidth=2, and burst length BL=16 areissued along with the read command RD (or write command WR).

FIG. 60 shows an example of another arrangement of the reference imageareas on the memory map. In this figure, the reference image area RIMGextends across adjacent page areas 14-0 and 14-1. Specifically, thereference image area RIMG exceeds a boundary 600 of the page area. Inthis case, if the memory has the multi-bank access function described inFIG. 7, by issuing the multi-bank access information SA′, an access canbe made using the active command once. In the case where the memory doesnot have the multi-bank access function, the active command needs to beissued a number of times to the banks BANK 0 and 1 to make an access.Therefore, the memory controller previously needs to set, in theregister, whether the image memory to be controlled has the multi-bankaccess function or not, and then the access control to the image memoryneeds to be changed in response to this set information.

FIG. 61 is a timing chart of the memory controller with respect to thememory without the byte boundary functions. This is an example of accessto the reference image RIMG shown in FIG. 59. A conventional SDRAM isnot provided with the byte boundary functions. In this case, the memorycontroller has to perform control shown in FIG. 61.

In FIG. 61, there are shown signals 610 exchanged between the referenceimage reading controller and the memory controller, and signals 611exchanged between the memory controller and the image memory. Asdescribed above, the reference image reading controller 514 sends to thememory controller the information on the upper-left coordinate POSX,POSY, width SIZEX and height SIZEY along with an access request REQ tothe memory, and the memory controller then returns an acknowledge signalACK in response to the sent information. It is assumed that the memorymapping information and the address of the upper-left origin of theframe image are set in the setting register beforehand.

In response to this access request REQ, the memory controller issues anactive command ACT, bank address BA=0, and row address RA=0 to the imagememory, and causes the memory to perform active operation. Thereafter,the memory controller issues an read command RD, bank address BA=0, andcolumn address CA=5, 6, 7 through 117, 118, 119 (24 times) insynchronization with a clock CLK, and receives 4-byte data twenty-fourtimes. Then, the memory controller changes the level of a strobe signalSTB to H level, and sends the received data to the reading controller.

FIG. 62 is a timing chart of the memory controller with respect to thememory having the byte boundary functions. This figure shows an exampleof access to the reference image RIMG shown in FIG. 59, and is a controlperformed when the memory has the byte boundary functions. In thefigure, there are shown signals 620 exchanged between the referenceimage reading controller and the memory controller, and signals 621exchanged between the memory controller and the image memory.

In this case, the same signal as the one shown in FIG. 61 is sent fromthe reference image reading controller to the memory controller. Thememory controller issues an active command ACT, bank address BA=0, androw address RA=0 to the image memory, and causes the memory to performactive operation. Thereafter, the memory controller issues an readcommand RD, bank address BA=0, column address CA=5, 6 through 117, 118(16 times), and start byte signal SB=01, and receives 4-byte datasixteen times. Furthermore, the memory controller changes the level of astrobe signal STB to H level, and sends the received 64-byte data to thereading controller. Since the memory has the byte boundary functions,the read command may be issued only sixteen times, improving the accessefficiency.

Also, although not shown, in the memory having the automatic internalcolumn address generating function shown in FIGS. 42 through 44, thecolumn address wrap width CAWrap=16 may be set beforehand, and thestarting column address CA 5, start byte signal SB=01, rectangular widthRwidth=2, and burst length BL=16 may be issued along with a read commandRD. In response to this issuance, the image memory internally generatescolumn address automatically, and outputs 4-byte data of the rectangulararea in 16 cycles. The memory controller receives the 4-byte datasixteen times continuously.

FIG. 63 is a timing chart of the memory controller with respect to thememory without the byte boundary functions and the multi-bank accessfunction. This example is an example in which the reference image RIMGshown in FIG. 60 is accessed, and shows a control performed on the imagememory that does not have the multi-bank access function. In the figure,there are shown signals 630 exchanged between the reference imagereading controller and the memory controller, and signals 631 exchangedbetween the memory controller and the image memory.

As shown in FIG. 45, the memory without the multi-bank function cannotaccess an area across a bank boundary. In this case, therefore, thememory controller issues an active command ACT, BA=0 and RA=0, to havethe page area 14-0 perform active operation, further issues a readcommand RD, bank address BA=0, and column addresses CA=15 through 127,and receives 8 bytes of data. Moreover, the memory controller issues anactive command ACT, BA=1, and RA=0, to have the page area 14-1 performactive operation, further issues a read command RD, bank address BA=1,and column addresses CA=0, 1 through 112 and 113, and receives 16 bytesof data. The memory controller then sends the receive 24-byte data tothe reference image reading controller.

FIG. 64 is a timing chart of the memory controller with respect to thememory having the multi-bank access function and the byte boundaryfunctions. This figure is also an example in which the reference imageRIMG shown in FIG. 60 is accessed. In the figure, there are shownsignals 640 exchanged between the reference image reading controller andthe memory controller, and signals 641 exchanged between the memorycontroller and the image memory.

The memory controller issues a bank address BA=0, row address RA=0, andmulti-bank access information SA′=10 (showing an access to two adjacentbanks in a lateral direction) along with an active command ACT. Inresponse to this issuance, the image memory performs active operation onthe bank BA=0. The memory controller then issues start byte signalSB=01, bank address BA, and column address CA sequentially along with aread command RD. In response to this column address CA=15, the imagememory performs active operation on the bank of BA=1. The memorycontroller receives 16 bytes of data in response to the read command RDissued 16 times. Moreover, the memory controller sends the received16-byte data to the reference image reading controller.

In this manner, the memory controller may issue the active command onceto the memory having the multi-bank access function, even in the case ofdata across a different bank boundary.

FIG. 65 is a flowchart of the control operation of the memorycontroller. First, a host CPU sets ON/OFF of the multi-bank activefunction in the setting register within the memory controller (S1). Thereference image reading controller computes the coordinate of areference image block (POSX, POSY) and the size (SIZEX, SIZEY) on thebasis of the motion vector information, macroblock division information,and target macroblock information (S2), and issues a rectangular accessrequest to the memory controller along with the rectangular accessparameters for the rectangular access (S3).

The memory controller computes BA, RA, CA, SB and SA′ to be issued whenmaking the rectangular access, on the basis of these rectangularparameters (POSX, POSY) (SIZEX, SIZEY), and the memory map informationand information on the frame image address that are set in the settingregister (S4). When the multi-bank active function is ON (YES in S5),the memory controller receives read data while issuing the BA, RA, andSA′ along with an active command ACT and further issuing the BA, CA, andSB along with a read command RD (S6, S7 and S8). In the case of thewrite operation, the memory controller outputs write data whilesequentially issuing the BA, CA and SB along with a write command WRinstead of a read command.

Moreover, when the multi-bank active function is OFF (NO in S5), thememory controller checks whether or not the requested rectangle extendsacross the page area, i.e., bank (S9). If the rectangle does not extendacross the bank (NO in S9), the memory controller receive the read datawhile issuing BA and RA along with the active command ACT and furtherissuing BA, CA and SB along with the read command RD sequentially (10,11 and 12). In the case of the write operation, the memory controlleroutputs write data while sequentially issuing the BA, CA and SB alongwith a write command WR instead of a read command.

Furthermore, if the rectangle extends across the bank (YES in S9), thebyte boundary functions cannot be used, hence the memory controllercomputes the coordinate POSX and the width SIZEX of the enlargedrectangular area E-RIMG shown in FIG. 56, and computes addresses BA, RAand CA of the upper-left coordinate corresponding to the computedcoordinate and width (S13). Then, the memory controller receives theread data while issuing BA and RA along with the active command ACT andfurther issuing BA and CA along with the read command RD to the enlargedrectangular area (S15, 16 and 17). Then, once reading of the upper-leftcoordinate within the bank is completed (YES in S17 and YES in S14), aprecharge command is generated once. Thereafter an active command isgenerated to the next bank, and the read data is received while issuingBA and CA along with the read command RD sequentially (S19, S16 and 17).Once all data items within the bank are received (YES in S17) andreading of all data items is finished (S18), the memory control isended.

It should be noted that when the byte boundary functions are set to OFFin the setting register of the memory controller, the memory controllerissues the active command, read command, and required addresses byperforming the configurations S13 through S18 of FIG. 65, as in FIG. 61.

In this manner, the memory controller can set ON and OFF of the byteboundary functions and ON and OFF of the multi-bank active functionsinto the built-in setting register, and appropriately issues requiredcommands and addresses, as well as the multi-bank information, startbyte information, and byte combination information such as the up mode,down mode and alternative, in accordance with the functions of the imagememory to be controlled.

FIG. 66 is a flowchart of the control operation of the memorycontroller. In this example, the memory controller can set whether ornot the image memory to be controlled has a function of switching theinput/output data in accordance with the endians shown in FIGS. 35 and36. First, into the setting register of the memory controller, the hostCPU sets the presence of an output data rearranging function within theimage memory (S20). The reference image reading controller then computesthe coordinate of the reference image block (POSX and POSY) and the size(SIZEX and SIZEY) on the basis of the motion vector information,macroblock division information, and target macroblock information(S21), and issues a rectangular access request to the memory controlleralong with the rectangular access parameters for the rectangular access(S22).

Next, the memory controller computes BA, RA, CA, SB and SA′ to be issuedwhen making the rectangular access, on the basis of these rectangularparameters (POSX and POSY) (SIZEX and SIZEY), and the memory mapinformation and information on the frame image address that are set inthe setting register (S23). Then, when the output data rearrangingfunction is set to ON (YES in S24), the memory controller issues thebank address BA, row address RA and multi-bank information SA′ alongwith the active command, and further issues the bank address BA, columnaddress CA, and start byte information SB along with the read command(S25). Thereafter, the memory controller repeatedly issues the readcommand, BA, CA, and SB until reading of all data items is finished (S26and S27).

On the other hand, when the output data rearranging function is set toOFF (NO in S24), the memory controller issues the bank address BA, rowaddress RA, and multi-bank information SA′ along with the activecommand, and further issues the bank address BA, column address CA, andstart byte information SB along with the read command (S25). Thereafter,the memory controller repeatedly issues the read command, BA, CA, and SBuntil reading of all data items is finished, and rearranges the dataitems so that the received data items are arranged in order of theoriginal image data items (S28, S29 and S30).

FIGS. 65 and 66 described above can be combined appropriately inaccordance with the set items in the setting register.

It should be noted that the present embodiment explains an example ofthe image memory that stores digital image data in which image dataitems of a plurality of pixels are arranged two-dimensionally. However,the present invention can applied to not only the image memory forstoring image data, but also a memory device that storestwo-dimensionally arranged data, other than image data, on the basis ofa predetermined mapping rule. When the stored data items are arrangedtwo-dimensionally, in the case where an arbitrary rectangular areawithin the two-dimensionally arranged data is accessed, sometimes thedata extending across a plurality of memory unit areas needs to beaccessed. In this case as well, the present invention can be applied.

<<Multi-Bank Access>>

Next, there is described multi-bank access for preventing the decreaseof access efficiency caused when accessing a rectangular area having aplurality of page areas as a problem of the rectangular access. Themulti-bank access function involved in rectangular access has beenalready described with reference to FIG. 7.

FIG. 67 is a schematic explanatory diagram of multi-bank accessaccording to the present embodiment. An access made to a rectangulararea with respect to the image memory is generated in an arbitraryplace. Therefore, in some cases, the rectangular access area 22straddles the boundaries of page areas in the memory map 12, as shown inFIG. 67. In the example shown in FIG. 67, the rectangular access area 22includes four page areas (page area of BA3 and RA0, page area of BA2 andRA1, page area of BA1 and RA4, and page area of BA0 and RAS).

According to the memory mapping 12, page areas that are adjacent to eachother horizontally and vertically are allocated to different banks.Therefore, in order to access the rectangular area 22 shown in FIG. 67,the four banks Bank 0 through Bank 3 within the memory device 86 have tobe accessed in order of Bank 3, Bank 2, Bank 1 and Bank 0. In an SDRAM,once the bank address BA and row address RA are specified and an activecommand is supplied, the word lines within a bank of the SDRAM (pageareas) are activated. Thereafter, the memory unit areas within theactivated page areas are accessed in response to a read command or writecommand specifying a bank address BA and column address CA. For thisreason, in order to access the rectangular access area 22, the memorycontroller has to issue the active command for the four banks to thememory device four times. Such memory control results in a decrease ofthe access efficiency.

In the present embodiment, therefore, the memory device is set into amode register that incorporates therein raw address step informationRS=4 (a reference numeral 671 in the figure) supplied along with acommand, in response to an extended mode register set command EMRS (areference numeral 670 in the figure), as shown in the timing chart inFIG. 67. The row address step information RS indicates the number atwhich the row addresses RA are wrapped around in a row direction in thememory mapping 12. In the example shown in FIG. 67, since the rowaddresses RA0-RA3, RA4-RA7 are wrapped around, RS is 4. Since the memorymapping 12 is not changed frequently in a normal image system, the rowaddress step information RS is preferably set into the mode registerwithin the memory device, when the image system is activated.

Once a rectangular access is generated, the memory device is suppliedwith a bank address BA=3, row address RA=0 and multi-bank informationSA′=4 (a reference numeral 673 in the figure) along with an activecommand ACT (a reference numeral 672 in the figure). More specifically,once the memory controller detects that the rectangular area to beaccessed straddles the four page areas on the memory map, i.e., that theaccess needs to be made to the four banks, the memory controllersupplies the number of access target banks, namely “4”, as themulti-bank information SA′ to the image memory device, in response to arectangular access request sent from the image processing unit.

In response to this active command ACT and the multi-bank informationSA′, the memory device activates, the bank BA3, the bank BA2 adjacentthereto in the row direction, the bank BA1 adjacent to the same in thecolumn direction, and the bank BA0 in the lower right. In this case, therow controller within the image memory generates a bank activationsignal for each of the plurality of banks, and further generates a rowaddress as a target of active operation within each bank, on the basisof the bank address BA=3, row address RA=0 and multi-bank informationSA′=4 that are supplied along with the active command ACT, as well asthe row address step information RS=4 that is stored in the moderegister. According to the memory mapping 12 shown in the figure, thefour row addresses as the target of active operation are, respectively,RA, RA+1, RA+RS, RA+RS+1, with respect to the supplied row address RA.These four row addresses are supplied to the corresponding four banks inresponse to the supplied bank address BA. Then, the plurality of bankswithin the memory device perform active operation on the basis of thebank activation signals and row addresses generated within the imagememory.

Therefore, in the example shown in FIG. 67, a total of four page areas,namely the page area of BA3 and RA0, the page area of BA2 and RA1, thepage area of BA1 and RA4, and the page area of BA0 and RA5, areactivated in response to the single active command ACT. In specificoperation of activation, the word lines WL are activated, the senseamplifiers are activated, and the potentials of the bit linescorresponding to the data items within the memory cells respectively areamplified.

Then, the memory device repeatedly supplies read commands RD (areference numeral 674 in the figure) along with the bank address BA andthe column address CA, and reads the data item of the correspondingmemory unit area specified by a bank address BA and a column address CA,in response to each of the read commands. In the case of a writecommand, the memory device writes the data item to a memory unit areacorresponding to a bank address BA and a column address CA that aresupplied along with a write command. In the example shown in FIG. 67,the bank addresses BA=3, 2, 1 and 0 are supplied along with the fourread commands RD, and column accesses are made sequentially to the fourbanks.

In this manner, according to the multi-bank access function of thepresent embodiment, the memory device responds to a single activecommand (first operation command) to perform active operation on thepage areas of a plurality of access-target banks beforehand, on thebasis of the bank address BA and row address RA to be supplied, themulti-bank information SA′, and the row address step information RS thatis set in advance. Therefore, in a subsequent column access, a bankaddress BA and a column address CA are supplied along with a readcommand or a write command properly, whereby the rectangular access isperformed.

It should be noted in the example shown in FIG. 67 that the memorydevice calculates row addresses of a plurality of banks on ground of therow address step information RS=4 in the memory mapping 12. Therefore,if the memory mapping 12 is different, then the arithmetic expressionfor obtaining row addresses is also different accordingly. Thus, memorymapping information can also be set along with the row addresses bymeans of the extended mode register set command EMRS. Alternatively,bank address bits may be shuffled in accordance with the memory mappinginformation to calculate row addresses corresponding to predeterminedmemory mapping in the memory device.

Also, in the example shown in FIG. 67, although the multi-bankinformation SA′ indicates 4, in the case in which SA′=2 representing twobanks in a lateral direction, SA′=3 representing two banks in verticaldirection, or SA′=1 representing per unit bank is supplied, the relevantbanks are activated respectively. The abovementioned multi-bankinformation SA′ indicating four types consists of two bits.

FIG. 68 is a figure for explaining the multi-bank access according tothe present embodiment. In FIG. 68, the rectangular area 22 is theaccess-target area. This rectangular access area 22 has four page areas,namely four banks 14-0, 14-1, 14-2 and 14-3, and is 2 clocks wide (8bytes) in the lateral direction by 8 rows high in the vertical directionwith the memory unit area of BA3, RA2, CA127 at the top. Therefore, themulti-bank information SA′ for specifying the rectangular access area 22may be either a) size information of the rectangular area (=width W,height H) or b) information on the number of banks (=4), which are shownin the figure.

The operation of the memory device corresponding to the above-describedtwo types of multi-bank information SA′ is described hereinafter withreference to FIG. 69 and FIG. 70.

FIG. 69 is a timing chart for the case in which the multi-bankinformation SA′ is the information on the number of banks (=4). FIG. 69shows the timing chart of FIG. 67, including column addresses CA (areference numeral 691 in the figure) of output data for four bytes BY 0through 3 of the input/output terminals DQ, as well as an access state(activation state) of each of the banks Bank 0 through 3 (a referencenumeral 690 in the figure).

First of all, the memory device sets step number data RS=4 of the rowaddresses in the memory mapping to the mode register by means of theextended mode register set command EMRS. Then, in response to the bankaddress BA3 and row address RA2 for specifying the leading page area, aswell as the multi-bank information SA′=4 (a reference numeral 673 in thefigure), the bank address BA3, row address RA2 and the multi-bankinformation SA′ being supplied along with the active command ACT, thememory device generates row addresses RA7, 6 and 3 within the four banksBank 0 through 3, and performs active operation on the page areascorresponding to the four row addresses including the supplied rowaddress RA2 (a reference numeral 690 in the figure). As a result, thefour banks enter an active state and memory access thereto is nowpossible within the memory device.

Thereafter, addresses BA3/CA127, BA2/CA124, BA1/CA3, BA0/CA0 and thelike are supplied along with sixteen read commands RD (a referencenumeral 674 in the figure), in response to which the memory deviceoutputs 4 bytes of data from the corresponding banks to the input/outputterminals DQ respectively, after a predetermined latency.

Supply of SA′=4 as the multi-bank information SA′ proves that an accessis made to a 2×2 page area, so that the memory device can execute activeoperation on the four banks in response to the active command ACT.Moreover, once the row address RA of the leading bank is supplied, rowaddresses of the rest of the banks can be calculated on the basis of therow address step information RS.

FIG. 70 is a timing chart for the case in which the multi-bankinformation SA′ is the size information of the rectangular area (W=8bytes, H=8 rows). This timing chart also shows the input/outputterminals DQ and an access state of each of the four banks Bank 0through 3.

The row address step number data RS=4 (a reference numeral 671 in thefigure) and step number data of the column addresses within the pagearea, CST=128 (a reference numeral 677 in the figure), are set into themode register by means of the extended mode register set command EMRS.Further, the bank address BA3 and row address RA2 are supplied alongwith the active command ACT (a reference numeral 672 in the figure), andthe size information 8×8 of the rectangular access area (a referencenumeral 676 in the figure) is supplied as the multi-bank information SA′(a reference numeral 675 in the figure). In response to this activecommand, the memory device performs active operation on the page areahaving the supplied addresses BA3 and RA2 (a reference numeral 700 inthe figure). The memory device then obtains the rest of the banks Bank0, 1 and 2 to be accessed, and the row addresses thereof RA 7, 6 and 3on the basis of the step number data CST=128, the column address CA127supplied along with the first read command RD, and the rectangle sizeinformation 8×8, and performs active operation on the page area of eachof these banks (a reference numeral 701 in the figure).

Thereafter, the memory device outputs 4 bytes of data from each of thecorresponding banks to the input/output terminals DQ (a referencenumeral 702 in the figure) in response to the sixteen read commands (areference numeral 674 in the figure).

In this manner, when the rectangle size is supplied as the multi-bankinformation SA′, the memory device determines whether access is madeacross a plurality of banks, on the basis of the supplied columnaddresses and memory mapping (column address step number CST), generatesan activation signal for each bank that is a target of active operation,as well as a row address of each bank, and performs active operationsequentially. Therefore, activation operation is performed on the banksBank 0, 1 and 2 after the leading column address CA=127 is supplied.

FIG. 71 is a configuration diagram of the memory device having themulti-bank access function. This figure is same as the configurationdiagram of the memory device shown in FIG. 9. In the memory device 86,the row controller 87 has, in order to realize the multi-bank accessfunction: a multi-bank activation controller 88 that generates pulsedbank activation signals actpz 0 through 3 provided to the banks to beactivated; and a row address calculator 97 that generates row address RAof each bank, which is to be activated. Also, the memory device hasspecial terminals SP0 and SP1 for supplying the multi-bank informationSA′.

A command controller 95 decodes a command that is supplied from acombination of signals RAS, CAS, WE and CS specifying commands. The rowaddress step number data RS of the memory mapping is supplied along withthe extended mode register set command EMRS from address terminals Add,and the row address step number data RS are set into a mode register 96.In this case, the type of data that is set is specified by a bankaddress BA, and the step number data RS is set into a register areacorresponding to this bank address BA.

The command controller 95 generates an active pulse actpz instructingfor start of operation on the row side, in response to the activecommand ACT. The multi-bank activation controller 88 distributes thisactive pulse actpz to the banks to be activated, which are determinedfrom the supplied bank address BA and the multi-bank number data SA′.This pulse signal to be distributes is the bank activation signals actpz0 through 3. The multi-bank information SA′ is inputted from the specialterminals SP0 and SP1 when the active command ACT is issued. Also, therow addresses RA are inputted from the address terminals Add.

Moreover, the row address calculator 97 generates four row addresses RA,RA+1, RA+RS, and RA+RS+1 on the basis of the bank address BA and rowaddress RA to be supplied, the step number data RS set in the moderegister 96, and the memory mapping. Then, these four row addresses aresupplied to a group of 2×2 banks having a bank with the supplied bankaddress BA on the upper left portion.

Each of the banks has a memory core having a memory array MA and adecoder Dec, and a core controller (not shown) that controls the memorycore. The core controller performs activation control to the memory corewithin each bank in response to the bank activation signals actpz 0through 3 described above. In this case, the abovementioned bank addressBA is supplied to each row decoder, the corresponding word lines aredriven, and then a group of sense amplifiers are activated. This is theactivation operation (active operation) performed in the banks.

Hereinafter, operation of selecting banks to be activated within thememory device, control of the timing of bank activation, row addressgenerating operation, and bank allocation setting operation in thememory mapping are specifically described as the functions required inthe multi-bank access.

[Selecting Banks]

FIG. 72 and FIG. 73 are figures showing a first example of themulti-bank activation controller 88. FIG. 72 shows a configuration ofthe multi-bank activation controller 88 and a timing chart. In the firstexample, 2 bits of bank number data are supplied as the multi-bankinformation SA′.

The timing chart is same as the abovementioned example, wherein, alongwith the extended mode register set command EMRS, a register settingdata V and the step number data RS are inputted to a bank addressterminal BA and an address terminal ADD respectively, and then set intothe mode register. Furthermore, a bank address BA, a row address RA, andthe multi-bank information SA′ are inputted along with the activecommand ACT.

The memory device latches the multi-bank information items SA′ 0, 1 andbank addresses BA 0, 1 that are inputted to each input buffer 94 to alatch circuit 720 in synchronization with a clock CLK. The multi-bankactivation controller 88 has a bank decoder 88A that decodes the bankaddresses BA 0 and 1 to generate four bank selection signals bnkz<3:0>,and a bank active pulse output circuit 88B that generates bankactivation signals actpz<3:0> allocated with the active pulses actpz, inresponse to the bank selection signals.

FIG. 73 shows a logical state of the bank decoder 88A corresponding to arectangular area to be accessed. FIG. 73(A) shows four types ofrectangular areas, and multi-bank information items SA′ (00, 01, 10, 11)corresponding thereto. FIG. 73(B) is a table showing logical processingperformed by the bank decoder. As shown, in the case of SA′=00, thenumber of activated banks is 1 and the bank decoder 88A—decodes the bankaddresses BA0 and BA1. Accordingly, the bank decoder 88A brings the bankselection signal bnkz<3:0> of only one bank selected by the suppliedbank addresses BA0 and BA1 to H level. Along with this operation, thebank activation signal actpz<3:0> is generated only in the selectedbank.

In the case of SA′=01, there are two banks to be activated in thehorizontal direction, thus the bank decoder 88A degenerates (ignores)the bank address BA0 and brings the bank selection signal bnkz<3:0> oftwo banks selected only by the bank address BA1 to H level. Along withthis operation, there is generated a bank activation signal actpz<3:0>of the bank selected by the supplied bank address and the adjacent bank,in the row direction.

In the case of SA′=10, there are two banks to be activated in thehorizontal direction, thus the bank decoder 88A degenerates (ignores)the bank address BA1 and brings the bank selection signal bnkz<3:0> oftwo banks selected only by the bank address BA0 to H level. Along withthis operation, there is generated a bank activation signal actpz<3:0>of the bank selected by the supplied bank address and the adjacent band,in the column direction.

In the case of SA′=11, there are a total of four banks to be activatedin the horizontal and vertical directions, thus the bank decoder 88Adegenerates (ignores) the bank addresses BA0 and BA1 and brings the bankselection signals bnkz<3:0> of all four banks to H level. Along withthis operation, there are generated bank activation signals actpz<3:0>of four banks adjacent to, in the row and column directions, the banksselected by the supplied bank address.

Degeneration of the bank addresses performed by the bank decoder is acontrol of bringing the corresponding bank addresses BA and inversionsignals/BA thereof to H level. Accordingly, the bank decoder 88A ignoresthese bank addresses and selects a bank by means of the remaining bankaddresses.

FIG. 74 and FIG. 75 are figures showing a second example of themulti-bank activation controller 88. FIG. 74 shows a configuration ofthe multi-bank activation controller 88 and a timing chart. In thesecond example, 3 bits of simultaneously-activated-bank data items SA′ 0through 2 are supplied as the multi-bank information SA′.

FIG. 75(A) shows a relationship of the memory mapping 12 to the bankaddresses BA0 and BA1. More specifically, with respect to the suppliedbank addresses BA0 and BA1, a bank on the right side can be selected byinverting the bank address BA0 and decoding it, a bank on the lower sidecan be selected by inverting the bank address BA1 and decoding it, and abank on the lower right side can be selected by inverting the both bankaddresses BA0 and BA1 and decoding them.

FIG. 75(B) shows the simultaneously-activated-bank data items SA′ 0through 2, banks to be selected, and logical processing performed by thebank decoder. More specifically, in the case of SA′0=H, the bank decoderinverts and inputs BA0 in order to select the right side bank inaddition to the bank selected by the supplied address. In the case ofSA′ 1=H, the bank decoder inverts and inputs BA1 in order to select thelower side bank in addition to the bank selected by the suppliedaddress. Furthermore, in the case of SA′2=H, the bank decoder invertsand inputs BA0 and BA1 in order to select the lower right bank inaddition to the bank selected by the supplied address.

Returning to FIG. 74, the multi-bank activation controller 88 has fourbank decoders 88A 0 through 3, an OR circuit 88C that subjects fourdecode signals of the bank decoders to a logical sum processing, and abank active pulse output circuit 88B. The active pulse output circuit88B is same as the one shown in FIG. 72. The four bank decoders 88A 0through 3 are, starting from the bottom, a decoder that decodes thesupplied bank addresses BA0 and BA1 to select an upper left bank, adecoder that inverts BA0 to select a bank on the right, a decoder thatinverts BA1 to select a bank on the lower, and a decoder that invertsboth BA0 and BA1 to select a lower right bank. Therefore, the top threebank decoders are activated in accordance with thesimultaneously-activated-bank data items SA′ 0 through 2 and outputs thecorresponding bank selection signals bnkz<3:0>.

According to the second example described above, the upper left leadingbank is selected by the supplied bank address, and the right, lower, andlower right banks are accordingly selected by 3 bits of simultaneouslyactivated-bank data items SA′ 0 through 2. Therefore, two banks in anoblique direction can be simultaneously activated, or three banks can besimultaneously activated, and a combination of banks to besimultaneously activated can be changed flexibly. Therefore, the secondexample can be accommodated to an access made to special areas.

FIG. 76 and FIG. 77 are figures showing a third example of themulti-bank activation controller 88. FIG. 76 shows a configuration ofthe multi-bank activation controller 88 and a timing chart. In the thirdexample, the rectangle size information W and H are inputted as themulti-bank information from the special input terminal SP. Therefore,the multi-bank activation controller 88 is provided with an activatingbank determination circuit 88D. The activating bank determinationcircuit 88D determines banks to be simultaneously activated, on thebasis of the step number data CST of column addresses within the pagearea, the rectangle size information W and H, and the column address CA.

As shown in the timing chart of FIG. 76, the memory device inputs thestep number RS of a row address in the memory mapping and the stepnumber data CST of a column address within a page area along with theextended mode register set command EMRS, and sets these, step number RSand step number data CST to the mode register. Next, the memory deviceinputs a bank address BA, a row address RA, and rectangular area sizedata W, H along with the active command ACT. At this moment, when theaddress of the memory device is inputted in a non-multiple manner, thecolumn address CA is also inputted along with the active command ACT.Since a general SDRAM inputs addresses in a multiple manner, the columnaddress CA is input-ted along with the read command or write command, asshown in FIG. 70.

The activating bank determination circuit 88D of the multi-bankactivation controller 88 determines bank to be simultaneously activated,on the basis of the step number data CST, the rectangle size informationW, H and the column address CA. This determination algorithm is shown inFIG. 77.

FIG. 77(A) shows information on the inside of a page area of memorymapping. Specifically, according to generalized memory mapping, when thecolumn address consists of M bits, CA[M-1:0], and the step numberCST=2^(S), the horizontal direction is mapped by a lower column addressCA[S-1:0] and the vertical direction is mapped by an upper columnaddress CA[M-1:S] in the page area 14. Specifically, the positions ofthe page areas 14 in the horizontal direction can be determined by thelower S bits of column addresses CA, and the positions of same in thevertical direction can be determined by the upper M−S bits, from thecolumn addresses CA to be inputted. Therefore, if the different betweenthe position of the horizontal direction within a page area and the stepnumber 2^(s) of the column address is smaller than the width W of therectangular area, it means that the rectangular area straddles the banksin the horizontal direction, and if the difference between the positionof the vertical direction and the height 2^(M-S) of the page area issmaller than the height H of the rectangular area, it means that therectangular area straddles the banks in the vertical direction.

As shown in the activating bank determination algorithm of FIG. 77(B),(1) the condition of straddling the banks (page areas) in the horizontaldirection is: 2S-CA[S-1:0]<W, and (2) the condition of straddling thebanks (page areas) in the vertical direction is: 2M-S-CA[M-1:S]<H, withrespect to the inputted column addresses CA.

To explain the example shown in FIG. 77(C), a page area 14X has 128memory unit areas that are selected by 7 bits of column address CA[6:0],wherein the step number CST in the row direction is 16. If, for suchpage area 14X, the input column address CA=77 (decimal numeral), therectangle size W=8 (8 clocks, 32 bytes) and H=8, the lower addressCA[3:0] is 13 and the upper address CA[6:4] is 4, thus it is determinedaccording to the above condition that the banks can be straddled in thehorizontal direction and the vertical direction.

The activating bank determination circuit 88D uses the above-describeddetermination algorithm to determine banks to be simultaneouslyactivated. As a result, the activating bank determination circuit 88Doutputs a bank address degenerate signal 88E to the bank decoder 88A.Specifically, in the case in which the banks in the horizontal directionare straddled, the bank address BA0 is degenerated, and in the case inwhich the banks in the vertical direction are straddled, the bankaddress BA1 is degenerated. This degenerate signal 88E is the same asthe multi-bank information SA′0, 1 shown in FIG. 72.

More specifically, in the third example, the activating bankdetermination function that the memory controller performs in the firstand second examples is provided in the memory device. If the activatingbank determination algorithm described above is provided within thememory controller, the multi-bank information SA′0, 1 shown in FIG. 72can be supplied from the memory controller to the memory device.

As described above, in order to realize the multi-bank activationfunction, the multi-bank activation controller 88 generates the bankselection signal bnkz<3:0> of a bank to be activated, on the basis ofthe input data, further generates the bank activation signal actpz<3:0>on the basis of the generated bank selection signal bnkz<3:0>, andcontrols the activation operation of the banks to be activated.

[Bank Activation Timing]

The multi-bank activation controller 88 supplies the bank activationsignal actpz<3:0> to banks to be activated, and each of the banks startsthe activation operation on a page area in response to this bankactivation signal. In this case, it is preferred to control the timingfor activating a plurality of banks. For example, a control forperforming the activation control on the plurality of bankssimultaneously, and a control for performing the activation operation onthe plurality of banks at different times can be considered. In theformer case, there are no restrictions on timings for inputting asubsequent read command or write command. In the latter case, on theother hand, the plurality of banks do not perform the activationoperation simultaneously, thus an instantaneous increase of consumedcurrent can be avoided.

FIG. 78 shows Example 1 of the bank activation timing. In this example,a plurality of banks are simultaneously subjected to the activationoperation. As described above, the multi-bank activation controller 88has the bank decoder 88A for selecting banks to be activated, and thebank active pulse output circuit 88B for distributing an active pulseactpz obtained from the command controller 95 to the selected banks, onthe basis of an activating bank selection signal bnk<3:0>. As shown inthe timing chart of the figure, the bank active pulse output circuit 88Bis constituted by four AND gates, and outputs the bank activationsignals actpz<3:0> at the same timing.

Each of banks bank 0 through 3 has a memory core 781 including a memorycell array, and a core control circuit 780 for controlling the memorycore. In response to the bank activation signals actpz<3:0>, each corecontrol circuit 780 activates a row decoder within the memory core 780,drives the word lines corresponding to the row addresses, and activatesa row of sense amplifiers.

In Example 1 shown in FIG. 78, a plurality of banks to be activated aresimultaneously subjected to active operation in response to the activecommand ACT, thus the subsequent read command or write command can besequentially inputted to access the plurality of banks.

FIG. 79 is a figure showing Example 2 of the bank activation timing. Inthis example, the plurality of banks are subjected to the activationoperation sequentially at different timings. The command controller 95has three delay circuits 791, 792, 793 in addition to a command decoder95A and a pulse forming circuit 95B. These three delay circuits areactivated in response to an activated-bank number signal 790, and delaythe active pulse actpz 0 generated by the pulse forming circuit 95B by apredetermined time period, to generate three delay active pulses actpz 1through 3. The active pulse actpz 0 and the delay active pulses actpz 1through 3 are supplied to each of four selectors SEL of the bank activepulse output circuit 88B.

The multi-bank activation controller 88 is constituted by an activatingbank control circuit 88C and the bank active pulse output circuit 88B.The activating bank control circuit 88C has incorporated therein thefunction of the bank decoder described above, determines an order ofperforming activation on banks to be activated, on the basis of thesupplied bank address BA[1:0] and the multi-bank data SA′[1:0], andsupplies a selection signal 795 to the selectors SEL. This selectionsignal 795 consists of 8 bits. Two bits of the selection signal aresupplied to each selector, and each selector outputs the bank activationsignal actpz<3:0> to the banks to be activated, in response to theselection signal 795.

It should be noted that the delay circuits 791 through 793 generate thenecessary delay active pulses actpz 1 through 3 in accordance with theactivated-bank number data 790, and thereby enables power saving.

FIG. 80 is a figure for explaining the logic of the bank activationtiming control performed by the activating bank control circuit 88C.FIG. 80 shows tables 800, 801 and 802 of the data on the order ofactivating the four banks (2 bits in binary display) for the case wherethe multi-bank data SA′[1:0]=11, 01, 10.

In the case in which the multi-bank data SA′[1:0]=11, all of the fourbanks are activated, and the activation order (00, 01, 10, 11) differsaccording to the supplied bank addresses BA[1:0], as shown in theactivation order data table 800. For example, in the case in which thesupplied bank address BA[1:0]=00, activation control is performed inorder of the banks Bank 0, 1, 2 and 3. The activation order data (8 bitsof 00, 01, 10, 11) shown in the table 800 corresponds to the 8-bitselection signal 795 that is generated by the activation bank controlcircuit 88C shown in FIG. 79. Specifically, each of the four selectorsSEL selects the active pulse actpz 0 and the three delay active pulsesactpz 1, actpz 2, and actpz 3. As a result, the bank activation signalsactpz <0> through <3> are generated sequentially.

Furthermore, in the case in which the supplied bank address BA[1:0]=01,the activation control is performed in order of the banks Bank 1, 0, 3and 2. The bank activation signals actpz <0> through <3> in this caseare shown in the timing chart of FIG. 79. The activation order data (8bits of 01, 00, 11, 10) shown in the table 800 is supplied as theselection signal 795 to the selectors, and each of the four selectorsSEL selects the delay active pulse actpz 1, active pulse actpz 0, anddelay active pulses actpz 3 and actpz 2, beginning at the top ofselectors. As a result, as shown in the timing chart, the bankactivation signals actpz <1>, <0>, <3> and <2> are generated in thisorder.

Similarly, in the case in which the multi-bank data SA′[1:0]=01, twobanks in the horizontal direction are activated, and, as shown in theactivation order data table 801, two activation order data items (00,01) are generated in response to the supplied bank addresses BA[1:0].

Similarly, in the case in which the multi-bank data SA′ [1:0]=10, twobanks in the vertical direction are activated, and, as shown in theactivation order data table 802, two activation order data items (00,10) are generated in response to the supplied bank addresses BA[1:0].According to this table 802, in order to activate the two banks, theactive pulse actpz 0 and the delay active pulse actpz 2 are used togenerate a bank activation signal, since the table 802 and thetable 800are in common. Specifically, as shown in a timing chart 803 below thetable 802, the internal active command ACT is generated at the timing ofthe active pulse actpz 0 and of the delay active pulse actpz 2 inresponse to a supplied active command ACT.

Therefore, in the case in which the multi-bank data SA′ [1:0]=10, theactivation order data (00, 01) shown in a table 804 may be generated, inplace of the one shown in the table 802. In this case, as shown in atiming chart 805 below the table 804, the internal active command ACT isgenerated at the timing of the active pulse actpz 0 and of the delayactive pulse actpz 1 in response to the supplied active command ACT.Specifically, the two banks to be activated simultaneously are activatedsuccessively at different timings.

FIG. 81 is a figure showing Example 3 of the bank activation timing. Inthis example, a plurality of banks are subjected to the activationoperation successively at different timings. In FIG. 81, in place of thedelay circuits 791 through 793 shown in FIG. 79, there are providedflip-flop circuits 810 through 812 that are operated in synchronizationwith the clock CLK. Other configurations are the same as those shown inFIG. 79. The activation bank control circuit 88C also is as described inFIG. 79 and FIG. 80.

According to this Example 3, since the delay circuits are the flip-flopcircuits 810 through 312 synchronized with the clock CLK, three delayactive pulses actpz 1 through 3 are generated from the active pulseactpz 0 at the delay timing synchronized with the clock CLK.Specifically, as shown in the timing chart of FIG. 81, the bankactivation signals actpz <0> through <3> are outputted sequentially insynchronization with the clock CLK. Accordingly, when the clock CLK isaccelerated, the bank activation signals actpz <0> through <3> followthe acceleration and are generated sequentially at high speed, and whenthe clock CLK is decelerated, the bank activation signals actpz <0>through <3> are generated sequentially at low speed accordingly.Therefore, clock synchronization can be operated.

[Generating Row Address]

The multi-bank access function of the present embodiment performsactivation control on all page areas of the banks required to beaccessed, in response to the active command ACT inputted once, a bankaddress, and a row address. Therefore, on the basis of the supplied bankaddress and row address, the banks required to be activated need to bedetermined, and row addresses need to be generated for specifying pageareas required to be activated.

FIG. 82 is a figure for explaining generation of row addresses in themulti-bank access of the present embodiment.

This figure shows the memory mapping 12, a logical value table 820showing supplied bank addresses BA 0, 1 corresponding to rectangularaccess areas RC 0 through 3, as well as a row address RA as a target ofactivating each bank. The memory mapping 12 is the same as the onedescribed above, wherein, in the page areas arranged in the row andcolumn directions, the banks of the page areas adjacent to each othervertically and horizontally are different from each other, and the rowaddress is incremented by one for every four banks Bank 0 through 3adjacent to one another vertically and horizontally.

According to this memory mapping 12, in the case of a rectangular areaRC0 to be accessed, it is evident from the supplied bank address BA=BA0(=00) and the supplied row address RA=RA0 that the addresses of pageareas to be activated simultaneously are BA0/RA0, BA1/RA0, BA2/RA0,BA3/RA0. In the case of a rectangular area RC1, it is evident from thesupplied bank address BA=BA1 (=01) and row address RA=RA0 that theaddresses of page areas to be activated simultaneously are BA1/RA0,BA0/RA1, BA3/RA0, BA2/RA1. In the case of a rectangular area RC2, it isevident from the supplied bank address BA=BA2 (=10) and row addressRA=RA0 that the addresses of page areas to be activated simultaneouslyare BA2/RA0, BA3/RA0, BA0/RA(0+RS), BA2/RA(0+RS). In the case of arectangular area RC3, it is evident from the supplied bank addressBA=BA3 (=11) and row address RA=RA0 that the addresses of page areas tobe activated simultaneously are BA3/RA0, BA2/RA(0+1), BA1/RA(0+RS),BA2/RA(0+RS+1).

To generalize the above addresses, in the case in which the supplied rowaddress is RA and the step number of the row address of the memorymapping 12 is RS, a row address to be generated in each of the banksBank 0 through 3 is as shown in the logical value table 820 in responseto the supplied bank addresses BA0, BA1. Specifically, the row addressesto be generated are as follows:

BA=00:RA, RA, RA, RA BA=01:RA+1, RA, RA+1, RA BA=10:RA+RS, RA+RS, RA, RABA=11:RA+RS+1, RA+RS, RA+1, RA

Therefore, the row address calculator 97 shown in FIG. 71 generates therow address shown in the logical value table 820 in each of the banksBank 0 through 3, in response to the supplied bank address BA and rowaddress RA.

FIG. 83 is a figure showing Example 1 of the row address calculatoraccording to the present embodiment. The row address calculator 97 has:address adders 831 through 834 for adding 0, 1, RS, RS+1 to the suppliedrow addresses RA; selectors SEL, each of which selects any of theoutputs of the address adders and supplies the selected output to anaddress decoder 836 of each bank; and a row address control circuit 830that supplies a selection signal 835 to the selectors SEL. The rowaddress control circuit 830 generates the selection signals (2 bitseach, 8 bits total) shown in the logical value table 821 of FIG. 82, inresponse to the bank addresses BA to be supplied. Moreover, the stepnumber data RS and RS+1 of the row address are supplied from the moderegister 96 to the address adders 833 and 834 respectively, and fixedvalues “0” and “1” are supplied to the address adders 831 and 832respectively. Accordingly, the adder 831 outputs the supplied rowaddress RA as it is.

For example, in the case in which the supplied bank address BA=01, therow address control circuit 832 generates “01, 00, 01, 00” as theselection signal 835, in response to which each of the selectors SELselects RA+1, RA, RA+1, RA, beginning at the top, and supplies theselected row addresses to the address decoders 836 of the banksrespectively. In the banks, the address decoders 836 of selected banksare activated in response to the abovementioned bank activation signalactpz<3:0>, the activated address decoders then decode theabove-described row addresses RA+1, RA, RA+1, RA, and corresponding wordlines are activated.

FIG. 84 is a figure showing Example 2 of the row address calculatoraccording to the present embodiment. In this example, the row addresscalculator 97 has four address adders 841 through 844 that add theconstant numbers 0, 1, RS, RS+1 selected by the selectors SEL to rowaddresses RA to be supplied, and the row address control circuit 830that supplies the selection signal 835 to the selectors SEL. The rowaddress control circuit 830 is the same as the one shown in FIG. 83.Then, in response to the selection signal of the row address controlcircuit 830, each of the selectors SEL selects any of the four constantnumbers 0, 1, RS, RS+1, and outputs the selected constant number to theaddress adders. Specifically, the row address computer 97 uses theselectors to select any of the constant numbers 0, 1, RS, RS+1 to beadded to the supplied row addresses RA, and sends the selected constantnumber to the address adders. The row address calculator 97 shown inFIG. 83 uses the selectors to select an output of any of the fouraddress adders, while the row address calculator 97 shown in FIG. 84uses the selectors to select any of the four constant numbers. This isthe only different between these row address computers.

As described above, the row address calculator 97 generates fournecessary row addresses from the row addresses RA to be supplied.Therefore, the memory device can internally generate the four necessaryrow addresses by inputting the row addresses by means of single activecommand, whereby a plurality of banks can be activated.

[Memory Mapping Setting]

In order to realize the multi-bank activation function, it is necessaryto set the memory mapping information in the memory device. For example,as described with reference to FIG. 82, banks to be activated in fourrectangular access areas RC 0 through 3 are selected based on the memorymapping 12, and row addresses to be generated are calculated. Therefore,if the memory mappings of the upper systems differ, the memory device isthen required to change the processing for determining the page areas tobe activated.

FIG. 85 is a figure showing two examples of memory mapping. A memorymapping 12A is the same as the memory mapping described previously,wherein banks Bank 0, 1 are arranged in the odd-numbered rows, banksBank 2, 3 are arranged in the even-numbered rows, and row addresses RAare arranged as shown. Further, as shown in a memory mapping 12B,even-numbered banks Bank 0, 2 are arranged in the odd-numbered rows,odd-numbered banks Bank 1, 3 are arranged in the even-numbered rows, androw addresses RA are arranged in the same manner as those of 12A.

FIG. 86 is a figure showing a bank address switching circuit 861 for twotypes of memory mapping described above. In the configuration diagram ofFIG. 86(B), the input buffer 94 is provided in a clock terminal CLK, aspecial input terminal SP0, and bank address terminals BA0, BA1, and alatch circuit 860 for latching signals in synchronization with the clockCLK is also provided.

As shown in the timing chart of FIG. 86(A), setting data V is inputtedfrom a bank address terminal BA, memory mapping information AR isinputted from the special terminal SP0, and step number data RS of a rowaddress is inputted from address terminals ADD, each of these inputsbeing inputted along with the extended mode register set command EMRS.Then, the setting data V, memory mapping information AR and step numberdata RS are set into the mode register 96.

In response to the memory mapping information AR set into the moderegister 96, the selectors SEL of the bank address switching circuit 861selects either 2-bit bank address BA0 or BA1 to generate an internalbank addresses ba0Z and ba1 z respectively. As shown in the figure, inthe case where memory mapping information AR=L, the internal bankaddresses are set into ba0 z=BA0 and ba1 z=BA1, and in the case wherememory mapping information AR=H, the internal bank addresses are setinto ba0 z=BA1 and ba1 z=BA0.

In this manner, by switching the bank addresses BA0, BA1 by means of theinput section on the basis of the memory mapping information AR, thebank selection function and row address generation function incorporatedin the memory device can be configured based on the common memorymapping 12A.

It should be noted in the above embodiment that although the multi-bankinformation (SA′), the simultaneously activated bank data (SA′ 0 through2), the rectangular area size data (W, H) and the like are inputted fromthe special input terminal SP, such input can be realized by unusedterminals. For example, in a read operation, if row addresses areinputted by the address terminals Add 0 through 12 and column addressesare inputted by the address terminals Add 0 through 9, the addressterminals Add 10 through 12 are not used when the column addresses areinputted. Therefore, these control data items SA′, W, H and the like canbe inputted from these unused address terminals Add 10 through 12 wheninputting the column addresses. The present invention can be applied tosuch a case.

Moreover, various information items that are set into the mode registerby the extended mode register set command EMRS are not limited to thedescriptions of the above embodiment, thus the applicable scope of thepresent invention comprises inputting these various information itemsfrom the address terminals.

<<Multi-bank Access and Byte Boundary>>

There has been described that the memory device has the byte boundaryfunction in order to respond to a rectangular access that across theboundary of memory unit area selected by bank address and columnaddress. There has also been described that the memory device has themulti-bank access function in order to respond to the case where arectangular access is made across the boundary of page area selected bybank addresses and row addresses. Here, in the case in which arectangular access area acrosses the boundary of page areas as well asmemory unit areas, the both functions can allow access to be made by asingle input of an active command and can eliminate unnecessary dataoutputs. Specific examples of this case are described hereinafter.

FIG. 87 shows a timing chart showing the case in which multi-bank accessand byte boundary are generated. The figure shows an example in whichthe rectangular access area 22 extends beyond page areas to straddle aplurality of banks BA3, BA2, BA1 and BA0, and further column accessextending beyond memory unit areas needs to be made. In this example,multi-bank information SA′=4 (=11) and start byte signal SB=2 are set.

FIG. 88 is a configuration diagram of the memory device having themulti-bank access function and byte boundary function. Although only twobanks Banks 2, 3 are shown in this memory device 86 for sake ofsimplicity, the memory device 86 is actually provided with two morebanks Banks 0, 1 that are not shown. The step number data RS of a columnaddress for memory mapping and the step number data CST of a columnaddress are set in the mode register 96 in advance.

As the row controllers, there are provided the multi-bank activationcontroller 88 that generates, from a bank address BA and multi-bankinformation SA′, bank activation signals actpz<3:0> of banks to beactivated, and row address calculators 97-2, 97-3 that calculate a rowaddress of each bank from a bank address BA, row address RA, and stepnumber data RS of the row address. These row address calculators 97-2,97-3 are each a part of the configurations described with reference toFIG. 83 and FIG. 84. Also, as described with reference to FIG. 78, thebank activation signals actpz are supplied to the core controller ofeach bank. However, illustration of the core controllers is omitted inFIG. 88.

The column controller 90 has column address controllers 290-2, 290-3that generate internal column addresses I-CA-2, 3 in each bank from acolumn address CA and bank address BA to be supplied, as well as fromthe start byte signal SB and the step number data CST of the columnaddress. These column address controllers 290 are the same as the columnaddress generating section shown in FIG. 44, and, by adding a bankaddress BA thereto, column addresses that are required at byteboundaries when the boundaries of the banks are straddled. It should benoted that the step number data CST is the same as the column addresswrap data CAWrap shown in FIG. 44.

Moreover, the column controller 90 generates a control signal S221 forselecting data of byte areas Byte 0 through 3 within each bank, on thebasis of the bank address BA and column address CA to be supplied, aswell as the start byte signal SB. The data latch circuits within thesefour byte areas Byte 0 through 3 within each bank are selected by thecontrol signal S221, and the selected data latch circuits are connectedto an input/output I/O bus. The configurations and operations of thebyte areas Bytes 0 through 3 within each bank are the same as thosedescribed with reference to FIGS. 22, 24 ad 29. Since each bank has fourbyte areas, the abovementioned control signal S221 is a selection signalconsisting of 4×4=16 bits.

The operation that is performed when the rectangular area 22 shown inFIG. 87 is accessed is described next. As shown in the timing chart ofFIG. 87, the step number data CST=4 (a reference numeral 871 in thefigure) of column addresses and the step number data RS=4 (a referencenumeral 872 in the figure) of row addresses are inputted along with theextended mode register set command EMRS, and set into the mode register96.

Next, bank addresses BA and row addresses RA of page areas with pixelsin the upper left portion of the rectangular access, as well asmulti-bank information SA′=4 (a reference numeral 873 in the figure),are inputted along with an active command ACT (a reference numeral 876in the figure). When SA′=4, simultaneous activation of 2×2=4 banks. Inresponse to this, the multi-bank activation controller 88 outputs thebank activation signals actpz<3:0> to these four banks. Furthermore, therow address calculators 97-2, 3 calculate a row address of each of thebanks. Then, row decoders of the four banks decode the calculated rowaddress to drive the corresponding word lines, and then the banks areactivated.

Thereafter, a bank address BA=3, a column address CA 126, a start bytesignal SB=2 (a reference numeral 874 in the figure), and secondinformation of the byte combination information BMR=UP (a referencenumeral 875 in the figure) are inputted along with a read command RD (areference numeral 877 in the figure). The column address controller290-3 of Bank 3 corresponding to this bank address BA generates a columnaddress CA=126, 127 on the basis of the supplied column address CA=126and the start byte signal SB=2, and outputs the column address CA=127 asthe internal column address I-CA-3. Accordingly, Bank 3 causes each ofthe byte areas Bytes 0 through 3 to output data on the column addresses126, 127. Then, in response to the control signal S221 inputted from adata latch selector 221, the byte areas Bytes 2, 3 and the byte areasBytes 0, 1 output the data on the column address CA=126 and the data onthe column address CA=127 to the I/O bus, respectively.

Next, the bank address BA=3, column address CA=127, SB=2, and BMR=UP areinputted along with the read command RD. In response to this, the columnaddress controller 290-3 generates the internal column addressI-CA-3=127, and Bank 3 outputs 4-byte data of the column address 127. Onthe other hand, the column address controller 290-2 detects, from thebank address BA=3, column address CA=127, and start byte signal SB=2,that the data needs to be read from Bank 2, and refers to the stepnumber data CST of the column address to output a column address CA=124of Bank 2 as the internal column address I-CA-2. Consequently, Bank 2reads 4-byte data of the column address CA=124. Then, the data latchselector 221 generates the control signal S221 on the basis of the bankaddress BA=3, column address CA=127, and start byte signal SB=2, and thedata on the byte areas Bytes 2, 3 and the data on the byte areas Bytes0, 1 are outputted from Bank 3 and Bank 2, respectively, to the I/O bus.

Subsequently, column addresses CA=2, 3, 6, 7, corresponding to the bankaddress BA=1 are inputted along with the read command RD, the columnaddress controllers 290 similarly generate required column addresses,the data latch selector 221 generate the required control signal S221,and 4-byte data of the position corresponding to the start byte signalSB=2 is outputted from the same bank or an adjacent bank.

Although the above description was about the operation of the readcommand, the same column access control is performed in the case of awrite command as well.

According to the present embodiment, with respect to the rectangularaccess that is made across page areas and straddles a plurality ofbanks, access can be made from arbitrary bytes (orbits) within a memoryunit area to 4-byte data (or 4-bit data), on the basis of the start bytesignal SB and the byte combination information BMR.

[Memory Controller Responding to Multi-Bank Access]

The memory controller for controlling the memory device having themulti-bank access function is described next. As described withreference to FIG. 69 and FIG. 70, the memory controller sets the stepnumber data RS of row addresses, the memory mapping information AR andthe like to the mode register within the memory device in advance,issues the active command ACT, bank addresses BA, row addresses RA, andmulti-bank information SA′ to the memory device in response to arectangular access request sent from the memory access source, andfurther issues the bank address BA and the column address CA-along withthe read command RD or write command WR. Therefore, the memorycontroller needs to generate the above addresses or data required forthe multi-bank access function, in response to a memory access request.The configurations and operations of such memory controller will bedescribed.

FIG. 89 is a figure showing an example of memory mapping. The memorymapping 12 corresponds to a frame image. As described above, in thismemory mapping 12, bank addresses BA0, 1 are allocated to theodd-numbered rows of the page areas 14 arranged in the form of a matrix,while bank addresses BA2, 3 are allocated to the even-numbered rows. Rowaddresses RA are incremented sequentially by one in each row, and therow address step number RS is RS=4. Each of the page areas 14 isconstituted by 16 pixels×32 rows, wherein a memory unit area consistingof data with four pixels (4-byte data) is specified by one columnaddress. Therefore, one page area 14 has 512/4=128 column address areas(memory unit areas).

In this memory mapping 12, eight page areas are arranged in thehorizontal direction, and four page areas are arranged in the verticaldirection. Therefore, in this memory mapping 12 the number of pixels inthe horizontal direction is 128 (=16 pixels×eight page areas), and thenumber of pixels in the vertical direction is also 128 (=32 rows×fourpage areas). Various computation processes are described hereinafterbased on this memory mapping.

FIG. 90 is a configuration diagram of the memory controller according tothe present embodiment. As with FIG. 54, the memory controller 82receives memory access requests from a plurality of access source blocks81-1 through 81-n, and performs access control on the memory device 86in response to the memory access requests that are permitted by thearbitration circuit 540. Specifically, the memory controller 82 hasinterfaces IF_1 through IF_n corresponding to the access source blocks81-1 through 81-n, and further has sequencers SEQ_1 through SEQ_ngenerating addresses and commands in response to the access requests.

Therefore, the interfaces IF_1 through IF_n exchange data with theaccess request source blocks 81. There are two types of accesses madefrom the access source blocks: horizontal access and rectangular access.The arbitration circuit 540 arbitrates the access requests sent from theinterfaces, and outputs an access instruction to the sequencer SEQ_nthat has acquired the access right. The selector SEL then selects acommand and address from the sequencers SEQ_1 through SEQ_n in responseto a selections signal S540 sent from the arbitration circuit 540, andoutputs the selected command and address to the memory device 86. Theselector SEL further selects a data line Data from the interfaces IF_1through IF_n in response to the selection signal S540.

In a register 543 various parameters are set from the host CPU. Theparameters include function data on whether the memory device 86 has thebyte boundary function and the multi-bank access function. In addition,configuration parameters include a row address of an upper left pixel onthe frame image ROW_BASE_ADR, the number of pixels in the horizontaldirection of the frame image PICTURE_MAX_XSIZE, and the like.

The memory device 86 is an image memory having the abovementioned byteboundary function and multi-bank access function. The memory controller82 and the memory device 86 shown in FIG. 90 configure the imageprocessing system.

FIG. 91 is a figure showing signals between the access source blocks andthe interfaces. FIG. 91(A) shows signals sent when the rectangularaccess is made, and FIG. 91(B) shows signals sent when the horizontalaccess is made. The access source block 81-n outputs an access requestsignal REQ and data on an access target area. Transmission of thesignals that is performed when both accesses are made is describedhereinafter.

FIG. 92 is a figure for explaining the data on the access target area.Data on the frame image FM-IMG is stored in a logical address space S86of the memory device. As described above, the row address of the upperleft pixel ROW_BASE_ADR of this frame image FM-IMG and the number ofpixels in the horizontal direction of the frame image PICTURE_MAX_XSIZEare set in the register 543. In the case in which a rectangular areaRIMG within this frame image is the access target area, a frame pixelcoordinates (X_POS, Y_POS) of the upper left pixel within the frame, thesize of the rectangular area in the horizontal direction X_SIZE, and thesize of the same in the vertical direction Y_SIZE are supplied from theaccess source block 81-n to the interface IF_n within the memorycontroller.

It should be noted that the frame image FM-IMG corresponds to the memorymapping 12 in FIG. 89. Specifically, the upper left pixel of the frameimage FM-IMG corresponds to the upper left pixel of a page area havingbank address BA=0 and local row address RA=0. Therefore, a row addressof the logical address space of the memory can be obtained from the rowaddress of the upper left pixel ROW_BASE_ADR of the frame image FM-IMGand the local row address RA within the frame.

FIG. 93 is a timing chart of the signals between the access sourceblocks and the interfaces. In the rectangular access (at the time ofreading) shown in FIG. 93(A), the access source block 81-n brings aread/write instruction signal RXW to H level (read), and outputs accesstarget area data X/Y_POS, X/Y_SIZE while asserting the access requestREQ. In response to this, the memory controller sends back anacknowledge ACK, performs access control on the memory device 86 after apredetermined arbitration processing is performed, and acquires readdata. Then, the interface IF_n of the memory controller outputs the readdata RDATA (Data (A0 through A7)) while asserting an enable signal EN.This enable signal EN is asserted one clock cycle ahead, and negated oneclock cycle in advance.

On the other hand, in the rectangular access (at the time of writing)shown in FIG. 93(B), the access source block 81-n brings a read/writeinstruction signal RXW to L level (write), and outputs access targetarea data X/Y_POS, X/Y_SIZE while asserting the access request REQ. Inresponse to this, the memory controller sends back an acknowledge ACK,performs access control on the memory device 86 after a predeterminedarbitration processing is performed, and receives write data WDATA (Data(A0 through A7)) while asserting an enable signal EN. This enable signalEN also is asserted one clock cycle ahead, and negated one clock cyclein advance.

In the case of the horizontal access as well, the access source blockssupply the leading address ADR of the horizontal access and horizontalaccess size SIZE, receive the read data RDATA in the case of reading,and output the write data RDATA in the case of writing. Specifically, asshown in FIG. 91, the access source blocks supply the horizontal accessleading address ADR, horizontal access size SIZE, and read/writeinstruction signal RXW, while asserting the access requests REQ. Inresponse to this, the interfaces sends back the acknowledge signal ACK.Then, the memory controller executes memory access, and outputs the readdata RDATA while asserting the enable signal. Furthermore, at the timeof writing, the memory controller receives the write data WDATA whileasserting the enable signal EN, before executing the memory access.

FIG. 94 is a figure showing schematic operation of the memorycontroller. The operation steps are executed in order of the referencenumerals 1 through 4. First, the access request source block 81-n issuesan access request REQ, and then, in response to this access request REQ,the interface IF_n transfers the access request to the arbitrationcircuit 540. Next, if the memory device 86 can be accessed, and thepriority of the access request source is the highest, the arbitrationcircuit 540 sends an acknowledge signal ACK to the interface IF_n, andoutputs a command issuance starting instruction START to the sequencerSEQ_n. In response to this command issuance starting instruction START,the sequencer SEQ_n receives various parameters such as X/Y_POS andX/Y_SIZE required for command issuance, from the interface IF_n.

The sequencer SEQ_n issues a command on the basis of the abovementionedparameters and the parameters set in the register, and begins accessingthe memory device 86. In accordance with the status of issuance of thecommand, the sequencer SEQ_n issues the enable signal EN correspondingto the amount of data, and this enable signal EN is transmitted to theaccess request source 81 _(—) n via the interface IF_n. In the case inwhich reading is performed, the read data is transmitted from the memorydevice 86 to the access request source 81 _(—) n via the interface IF_nin response to the enable signal EN described above. In the case inwhich writing is performed, the write data is transferred from theaccess request source 81 _(—) n to the memory device 86 via theinterface IF_n in response to the enable signal EN described above.

In this manner, during the access control process in which the commandis issued to the memory device 86, the sequencer SEQ_n asserts, to thearbitration circuit 540, an active signal ACTIVE indicating that thedata is being accessed. Once the access to the memory is ended, theactive signal ACTIVE is negated.

FIG. 95 is a configuration diagram of a sequencer SEQ. The sequencer SEQhas: a controller 940 for controlling the entire sequencer; anintermediate parameter generating section 941 that generates anintermediate parameter from the access target area data X/Y_POS,X/Y_SIZE transferred from the interface IF_n, the row address of theupper left pixel ROW_BASE_ADR of the frame image FM-IMG that is set inthe register 543, and the number of pixels PICTURE_MAX_XSIZE in thehorizontal direction of the frame image; and a command/addressgenerating section 942 that generates commands and addresses on thebasis of the intermediate parameter and output the commands andaddresses to the memory device 86.

FIG. 96 is a figure for explaining a computing equation used forgenerating the intermediate parameters. In this example, the rectangulararea RIMG within the frame image FM-IMG is accessed, as shown in FIG.96(A), and data items thereof are as follows:

PICTURE_MAX XSIZE=128

ROW_BASE_ADR=0

(X_POS, Y_POS)=(28, 94)

(X_SIZE, Y_SIZE)=(8, 4)

Moreover, FIG. 96(B) shows pixel numbers in the horizontal direction andpixel numbers (row numbers) in the vertical direction in four page areasBA1/RA4, BA0/RA5, BA3/RA4 and BA2/RA5 in the vicinity of the rectangulararea RIMG. These information items are generated as the intermediateparameter in the manner described below.

The intermediate parameter generating section 941 generates theintermediate parameter by means of the following computation.

(1) In the case in which the rectangular data RIMG straddles the fourpage areas, the upper left bank address BA can be obtained in the mannerdescribed next. In the following manner, first of all, the frame pixelcoordinates (X_POS, Y_POS) of the upper left pixel of the rectangulardata RIMG within the frame image FM-IMG are obtained, and thesecoordinates are divided by the number of horizontal pixels 16 and thenumber of vertical pixels 32 of the page area respectively, whereby abank X address BA_X_ADR and a bank Y address BA_Y_ADR are obtained. Eachremainder obtained in this division is rounded.

BA_X_ADR=X_POS/16

BA_Y_ADR=Y_POS/32

The bank X address BA_X_ADR and the bank Y address BA_Y_ADR eachindicates which page area in the horizontal direction or verticaldirection in the memory mapping 12 the upper left pixel of therectangular area corresponds. It should be noted that the upper leftportion of the memory mapping 12 is located at the 0^(th) page area inthe horizontal direction and the 0^(th) page area in the verticaldirection.

The following bank addresses BA[1:0] are obtained depending on whetherthe obtained bank X address BA_X_ADR and the bank Y address BA_Y_ADR areodd or even.

If the BA_X_ADR is an even number and the BA_Y_ADR is an even number,upper left BA=0

If the BA_X ADR is an odd number and the BA_Y ADR is an even number,upper left BA=1

If the BA_X_ADR is an even number and the BA_Y_ADR is an odd number,upper left BA=2

If the BA_X_ADR is an odd number and the BA_Y_ADR is an odd number,upper left BA=3

(2) The bank address BA on the right side, the bank address BA on thelower side, and the bank address BA on the lower right bank address BAare obtained as follows. Specifically, according to the memory mapping12, the right BA, lower BA, and lower right BA are obtained, as shownbelow, from the upper left BA[1:0] obtained in (1) described above. Itshould be noted that “˜” means an inverted bank address.

Right BA=[upper left BA [1], ˜upper left BA [0]]

Lower BA=[˜upper left BA [1], upper left BA [0]]

Lower right BA=[˜upper left BA [1], ˜upper left BA [0]]

According to the examples shown in FIG. 96, (X_POS, Y_POS)=(28, 94) isestablished, thus, for the upper left bank address BA,

BA_X_ADR=X_POS/16=28/16=1

BA_Y_ADR=Y_POS/32=94/32=2

are established. Also, since BA_X_ADR=1 is odd and BA_Y_ADR=2 is even,the upper left bank address BA[1:0]=01 is established. That is, BA1 canbe obtained.

Moreover,

The right BA, lower BA, lower right BA, BA0, BA3, BA2, can be obtainedfrom the upper left BA=2′b01, as follows.

Right BA=[upper left BA [1], ˜upper left BA [0]]=[00]=0

Lower BA=[˜upper left BA [1], upper left BA [0]]=[11]=3

Lower right BA=[˜upper left BA [1], ˜upper left BA [0]]=[10]=2

(3) An access start row address ROW_ADR within the logical address spaceS86 of the memory is as follows.

ROW_ADR=ROW_BASE_ADR+[PICTURE_MAX_XSIZE/(16*2)]*[Y_POS/(32*2)]+X_POS/(16*2)

Specifically, ROW_BASE_ADR is a row address of an upper left pixel ofthe frame image, PICTURE_MAX_XSIZE/(16*2) is the number of row addresssteps in the horizontal direction within the frame, Y_POS/(32*2)indicates at what number in the vertical direction within the frame theupper left pixel of the rectangular area RIMG is positioned (a referencenumeral 961 in FIG. 96), and X_POS/(16*2) indicates at what number inthe horizontal direction within the frame the upper left pixel of therectangular area RIMG is positioned (a reference numeral 962 in FIG.96).

According to the examples shown in FIG. 96, PICTURE_MAX XSIZE=128,ROW_BASE_ADR=0, and (X_POS, Y_POS)=(28, 94) are set, thusROW_ADR=ROW_BASEADR+[PICTURE_MAX_XSIZE/(16*2)]*[Y_POS/(32*2)]+X_POS/(16*2)=0+(128/32)*(94/(32*1))+28/(16*2)=4is established.

(4) An access start column address COL_ADR in the logical address spaceS86 of the memory is a column address within a page, and is obtained asfollows:

COL_ADR=4*Y_POS %32+(X_POS/4)%4

Here [%] is a remainder. Specifically, the number of steps of the columnaddress within the page area is 4, the number of columns in thehorizontal direction in the page area is 4, and the number of rows inthe vertical direction is 32, as shown in FIG. 89, thus Y_POS %32indicates the number of rows within the page area of BA1, RA4, and(X_POS/4) %4 indicates the number of columns within the page areas.

According to the examples shown in FIG. 96, the access start columnaddress can be obtained as follows:

$\begin{matrix}{{COL\_ ADR} = {{4*{Y\_ POS}\mspace{14mu} \% \mspace{11mu} 32} + {\left( {{X\_ POS}\text{/}4} \right)\mspace{11mu} \% \mspace{11mu} 4}}} \\{= {{4*94\% \mspace{11mu} 32} + {\left( {28\text{/}4} \right)\% \mspace{11mu} 4}}} \\{= {120 + 3}} \\{= 123}\end{matrix}$

(5) Next, since the number of pixels in the horizontal direction of apage area is 16 and the number of pixels within the vertical axis of apage area is 32, the X coordinate (BA_X_POS) and Y coordinate (BA_Y_POS)within the bank are obtained as follows:

BA_X P0S=X_POS %16

BA_Y_POS=Y_POS %32

The results correspond to the coordinates (BA_X_POS, BA_Y_POS) of theupper right pixel of the rectangular area RIMG within the upper rightbank (BA1/RA4) shown in FIG. 96(C).

(6) X-direction BANK straddling flag and Y-direction BANK straddlingflag indicating whether the rectangular area RIMG straddles a bank (pagearea) are obtained as follows from the X and Y coordinates within thebank, i.e., BA_X_POS, BA_Y_POS, which are obtained in (5), and the sizesof the rectangular area RIMG in the horizontal direction and verticaldirection, i.e., X/Y_SIZE:

If BA_X_POS+X_SIZE>15, X-direction BANK straddling flag=1

If BA_Y_POS+Y_SIZE>31, Y-direction BANK straddling flag=1

Specifically, as shown in FIG. 96(C), if the value that is obtained byadding the rectangular area size X/Y_SIZE to the coordinates (BA_X_POS,BA_Y_POS) of the upper left pixel of the rectangular area RIMG exceedsthe horizontal direction size 15 and vertical direction size 31 of thepage area, it means that the bank is straddled.

To describe the above (5) and (6) by means of the examples shown in FIG.96, the X coordinate and Y coordinate within the bank are as follows:

BA_X_POS=X_POS %16=28%16=12

BA_Y_POS=Y_POS %32=94%32=30

X-direction BANK straddling flag and the Y-direction BANK straddlingflag are as follows:

BA_X_POS+X_SIZE=12+8=20, which is higher than 15, thus X-direction BANKstraddling flag=1, and

BA_Y_POS+Y_SIZE=30+4=34, which is higher than 31, thus Y-direction BANKstraddling flag=1,

thus the bank is straddled by RIMG in both X and Y directions.

(7) Next, the sizes in X, Y directions of a rectangular area straddlingfour banks, i.e., 1ST_X_SIZE, 2ND_X_SIZE, 1ST_Y_SIZE, 2ND_Y_SIZE, arecomputed as follows:

As shown in FIG. 96(C), if BANK is straddled in X direction, the X_SIZEon the left side of the BANK is 1ST_X_SIZE, and on the right side is2ND_X_SIZE. If the BANK is straddled in Y direction, the Y_SIZE on theupper side of the BANK is 1ST_Y_SIZE, and on the lower side is2ND_Y_SIZE. If the BANK is not straddled, only 1STX_SIZE and 1ST_Y_SIZEare effective. Therefore,

If X-direction BANK straddling flag=1,

1ST_X_SIZE=16_BA_X_POS

2ND_X_SIZE=X_SIZE_(—)1ST_X_SIZE

If X-direction BANK straddling flag=0,

1ST_X_SIZE=X_SIZE

If Y-direction BANK straddling flag=1,

1ST_Y_SIZE=32−BA_Y_POS

2ND_Y_SIZE=Y_SIZE−1ST_Y_SIZE

If Y-direction BANK straddling flag=0,

1ST_Y_SIZE=Y_SIZE

When the examples shown in FIG. 96 are applied, since X-direction BANKstraddling flag=1,

1ST_X_SIZE=16-BA_X_POS=16−12=4

2ND_X_SIZE=X_SIZE−1ST_X_SIZE=8−4=4 and since Y-direction BANK straddlingflag=1,

1ST_Y_SIZE=32−BA_Y_POS=32−30=2

2ND_Y_SIZE=Y_XIZE−1ST_Y_SIZE=4−2=2

(8) Finally, the row address step information RS is the numberindicating how many row addresses increase when scanning the frame image12 (FM-IMG) from the left end to the right end in the horizontaldirection, and is obtained by the following equation:

RS=PICTURE_MAX_(—) XSIZE/(16*2)

In the examples shown in FIG. 96, RS is obtained as follows:

RS=PICTURE_MAX_(—) XSIZE/(16*2)=128/32=4

As described above, the intermediate parameter generating section 94computes the intermediate parameters (1) through (8) by means of theabove equations, and outputs the results to the command/addressgenerating section 942. Then, the command/address generating section 942generates a command, bank address BA, row address RA, column address CA,row address step information RS and multi-bank information SA′ to besupplied to the memory 86, on the basis of the intermediate parameters.

FIG. 97 is an operational flowchart of the command/address generatingsection. The figure shows generated command in an elliptical shape.First, the memory controller issues a normal mode register set commandMRS to perform various initial settings on the mode register within thememory device (S40). These initial settings are performed in a normalSDRAM. Then, the memory controller enters a standby state (S41). Then,when an access request is received from the access source block 81, theintermediate parameter generating section 941 generates theabove-described intermediate parameters from the access target area dataX/Y_POS and X/Y_SIZE that are received from the access source block, therow address of the upper left pixel within the frame image ROW_BASE_ADRand the number of pixels in the horizontal direction PICTURE_MAX_XSIZEthat are set within the register 543 (S42).

Since whether the memory device to be controlled has the multi-bankaccess function or not is set in the register 543, this matter ischecked (S43). If the multi-bank access function is not set, the normalcontrol operation is performed to repeatedly issue the active commandACT and read command RD (or write command) in accordance with the numberof banks (S44).

In the case in which the multi-bank access function is set, thecommand/address generating section 942 determines the number of banks onthe basis of a bank straddling flag Flag [X:Y] (S46). As a result, thecommand/address generating section 942 generates the multi-bankinformation SA′ [1:0] from the bank straddling flag Flag [X:Y]. Therelationship therebetween is as follows:

Flag [X:Y]=00 SA′[1:0]=00 (one bank is activated)

Flag [X:Y]=10 SA′[1:0]=01 (two banks are activated in the X direction)

Flag [X:Y]=01 SA′ [1:0]=10 (two banks are activated in the Y direction)

Flag [X:Y]=11 SA′ [1:0]=11 (four banks are activated)

Therefore, the command/address generating section 942 issues themulti-bank information SA′ along with the active command ACT, leadingbank address BA, and leading row address RA (S80, S70, S60, S50).

In the case in which the four banks are activated simultaneously, thecommand/address generating section 942 within the memory controllerissues the multi-bank information SA′=11 along with the active commandACT and row address RA (S50). Then, the command/address generatingsection 942 issues a read command or write command along with the columnaddress CA within the upper left bank (S51). This read or write commandis repeatedly issued while incrementing the column address a number oftimes, i.e., 1ST_X_SIZE=N times, corresponding to the access size in theX direction within the upper left bank. Moreover, a read command orwrite command is issued along with the column address CA within theright bank (S52). This read or write command is repeatedly issued whileincrementing the column address a number of times, i.e., 2ND_X_SIZE=Ntimes, corresponding to the access size in the X direction within theupper left bank. Then, the number of lines is incremented by one (S53),and the steps S51, S52 and S53 are repeated until the number of linesexceeds the 1ST_Y_SIZE, which is the access size in the Y directionwithin the upper left bank (S54).

Next, the command/address generating section 942 issues a read commandor write command along with the column address CA of the lower bank(S55). This read or write command is repeatedly issued whileincrementing the column address a number of times, i.e., 1ST_X_SIZE=Ntimes, corresponding to the access size in the X direction within thelower bank. Furthermore, a read command or write command is issued alongwith the column address CA of the lower right bank (S56). This read orwrite command is repeatedly issued while incrementing the column addressa number of times, i.e., 2ND_X_SIZE=N times, corresponding to the accesssize in the X direction of the right bank. Then the number of lines isincremented by one(S57), and the steps S55, S56 and S58 are repeateduntil the number of lines exceeds the 2ND_Y_SIZE, which is the accesssize in the Y direction within the lower bank (S58).

The command/address generating section 942 obtains the column address tobe issued along with the abovementioned read or write command, from theleading column address COL_ADR=123 and the column address step numberdata CST=4, which are the intermediate parameters, on the basis of thememory map.

In the case in which two banks are activated simultaneously in the Xdirection, the command/address generating section 942 within the memorycontroller issues the multi-bank information SA′=01 along with theactive command ACT and row address RA (S60). Then, a read or writecommand and a column address are issued N times to the upper left bank(S61), and a read or write command and a column address are issued Ntimes to the right bank (S62). These steps S61, S62 and S63 are repeateduntil the number of lines exceeds the 1ST_Y_SIZE (S64).

In the case in which two banks are activated simultaneously in the Ydirection, the command/address generating section 942 within the memorycontroller issues the multi-bank information SA′=10 along with theactive command ACT and row address RA (S70). Then, a read or writecommand and a column address are issued N times to the upper left bank(S71), and these steps S71 and S72 are repeated until the number oflines exceeds the 1ST_Y_SIZE (S73). Similarly, a read or write commandand a column address are issued to the lower bank (S74, S75, S76).

Finally, in the case in which only one bank is activated, thecommand/address generating section 942 within the memory controllerissues the active command ACT, row address RA, and multi-bankinformation SA′=00 (S80). Then, a read or write command and a columnaddress are issued N times to the upper left bank (S81), and these stepsS81 and S82 are repeated until the number of lines exceeds 1ST_Y_SIZE(S83).

As described above, once the access request REQ and access target areadata X/Y_POS, X/Y_SIZE are received from the access source block, thememory controller 82 generates the intermediate parameter from the rowaddress of the frame area ROW_BASE_ADR and the number of pixels in thehorizontal direction PICTURE_MAX_XSIZE that are set in the register 543,then determines the number of banks to be activated simultaneously,issues the multi-bank information SA′ corresponding to the result ofdetermination, and then activates the bank within the memory devicesimultaneously. Accordingly, a plurality of banks can be activated byissuing the active command once, whereby memory access can be performedefficiently.

FIG. 98 is a timing chart between the memory controller and the memorydevice. This is a timing chart showing the case in which access is madeto the rectangular area RIMG that straddles four banks as shown in FIG.96. First of all, the memory controller issues the extended moderegister set command EMRS and row address step information RS4, and setsrow address step information RS into the register within the memorydevice. Next, the memory controller issues the active command ACT, upperleft bank address BA1, leading row address RA4 and multi-bankinformation SA′ (1, 1). In response to this, four banks aresimultaneously activated in the memory device.

In the example shown in FIG. 98, the multi-bank information SA′ isinputted from the column address terminal CA. However, in the case inwhich the memory device adopts an address multiplex configuration forinputting the row address RA and column address CA from a common addressterminal, the multi-bank information SA′ needs to be inputted from thespecial terminals SP as shown in FIG. 72.

Furthermore, the memory controller repeatedly issues a read command RD,a bank address BA and a column address CA. As shown in FIG. 96(B), thebank address BA and the column address CA are as follows: (BA, CA)=(1,123), (0, 120), (1, 127), (0, 124), (3, 3), (2, 0), (3, 7), (2, 4). Inresponse to this, 4-byte data of the pixel coordinates (X_POS, Y_POS)shown in FIG. 98 is outputted from the 4-byte input/output terminals BY0 through 3 of the memory, and the memory controller receives these4-byte data items. In this manner, the active command ACT is issued onlyonce.

In the case in which a plurality of banks are activated by a singleactive command by means of the multi-bank access function, when the byteboundary function is used to access image data in the middle of a 4-bytearea, the memory controller issues a read or write command, a bankaddress BA, a column address CA, start byte information SB, and memorymap information BMR, as shown in FIG. 87. Accordingly, the memorycontroller can reduce the number of times that the read or write commandis issued, and can further receive or output, with a single access, thedata that is effective to all data buses.

It should be noted that the above embodiment has described an example ofan image memory that stores the digital image data in which image dataitems of a plurality of pixels are arranged two-dimensionally. However,the present invention can be applied to not only the image memory forstoring the image data, but also a memory device that can also storetwo-dimensionally arrayed data items besides the image on the basis ofpredetermined mapping rules. If the stored data items are arrangedtwo-dimensionally, sometimes the data items of a plurality of page areasneed to be accessed when accessing any rectangular area within thetwo-dimensionally arrayed data. The present invention can be applied insuch a case as well.

<<Background Refresh>>

The overview of the background refresh has been described with referenceto FIG. 6. Specifically, in the case in which the memory controllercauses the memory device to successively execute the access operation,such as horizontal access, on a specific bank over a predeterminedperiod of time, the memory controller specifies a bank that is notaccessed, and issues a background refresh command to cause the memorydevice to execute the refresh operation on the specified bank. Thememory controller then issues a normal operation command during thisrefresh operation, and thereby causes the memory device to execute thenormal access operation on the bank in which the refresh operation isnot performed.

FIG. 99 is a schematic explanatory diagram of the background refresh inthe present embodiment. FIG. 99(A) shows a background refresh operation,and FIG. 99(B) shows a configuration of the memory device. The memorydevice 86 has a first area 991 and a second area 992 within a memorycell area 990. The first and second areas 991 and 992 correspond to thebank areas, and each can perform the active operation, read and writeoperations, and pre-charge operation independently. Furthermore, thememory device 86 has an input circuit 995 for inputting operation codes993, 994 from the memory controller 82, and a control circuit 996 forcausing either one of the first and second areas 991 and 992 of thememory cell area to perform the refresh operation, and causes the otherone to perform the normal memory operation, in response to the operationcodes. The operation codes are commands that are issued by, for example,the memory controller. Alternatively, the operation codes are acombination of a command and a signal value of a specific inputterminal.

As shown in FIG. 99(A), the control circuit 996 starts a refreshoperation 997 on the first area 991 within the memory, in response tothe first operation code 993. This first operation code 993 correspondsto the background refresh command BREN shown in FIG. 6. Insynchronization with this first operation code 993, or before the firstoperation code 993 is issued, a refresh target area (first area) is set,and the number of refresh operations (refresh burst length) to beexecuted in response to a single background refresh command, and thenumber of blocks of the memory (refresh block count) to be refreshedsimultaneously in a single refresh cycle are also set. In response tothese settings, the control circuit 996 causes the refresh target area(first area) to execute the refresh operation 997.

The background refresh is performed only in a partial area within thememory device (first area). Therefore, in the case of an area other thanthe refresh target area, the normal memory operation can be performed inparallel with the background refresh. Then, the control circuit 996executes normal memory operation 998 corresponding to the secondoperation code 994, in the selected second area 992 in response to thesecond operation code sent from the memory controller. The secondoperation code 994 is, for example, an active command, read/writecommand, or the like. Specifically, the control circuit 996 causes thesecond area 992 to execute the normal memory operation 998 in responseto the second operation code 994 even prior to the completion of therefresh operation 997 executed by the first area 991. The controlcircuit 996 also causes the first area 991 to execute the refreshoperation 997 in response to the first operation code 993 even prior tothe completion of the normal memory operation 998 executed by the secondarea 992.

In this manner, in the background refresh of the present embodiment, therefresh operation in the first area and the normal memory operation inthe second area can be executed without waiting for the completion ofthe other operation. Accordingly, it can be prevented that by executingthe refresh operations in all areas within the memory device, the normalmemory operations are interrupted during the refresh operation period,and of the effective access efficiency is decreased.

FIG. 100 is a schematic explanatory diagram of the memory system inwhich the background refresh of the present embodiment is performed. Amemory system 1000 is constituted by the memory controller 82 and thememory device 86. The memory device 86 is the same as the one shown inFIG. 99, and the memory controller 82 is constituted by a refreshcontrol circuit 1001, a multiplexer MUX; and an output circuit 1004. Therefresh control circuit 1001 is provided with first and second controlcircuits 1002 and 1003 that perform the refresh control of the first andsecond areas 991 and 992 of the memory respectively. Specifically, inthe background refresh function, while the memory device causes eitherthe first or second area 991 or 992 to perform refresh operation, thememory device causes the other area to perform normal memory operation.In order to do so, it is required that the first and second areas 991and 992 be subjected to refresh control individually.

According to the memory refresh specification, the period of time inwhich all memory areas need to be refreshed, and the number of timesthat the refresh operation is performed are defined. For example, in a64 M-bit memory, “64 ms/4096 cycles” is defined. In this case, in orderto refresh all of the 64 Mbits of cells within 64 ms, the refreshoperation is performed at a frequency of every 15, 6 μs (=64 ms/4096),wherein 16 Kbits (=64M/4096) of cells are refreshed in one refreshoperation.

On the other hand, in the case in which the memory cell area 990 isconstituted by the first and second areas 991 and 992 as shown in FIG.100, all of the 32 Mbits of cells in each area need to be refreshed 2048times within 64 ms. Therefore, in order to perform the refresh operationon the first and second areas by randomly switching between the twoareas, the control circuits 1002 and 1003 for separately controlling thefirst and second area are required.

FIG. 101 is an operational flowchart of the memory controller forcontrolling the background refresh. In the image processing system, theimage processing device outputs a memory operation request to the memorycontroller, and a memory operation event occurs within the memorycontroller in response to the memory operation request. Moreover, arefresh processing event also occurs within the memory controller.Therefore, the memory operation event and the refresh processing eventneed to be adjusted. In the above example, in case of horizontal access,if the both events do not occur within the same area (bank), a commandfor one of the events can be issued even when the processing on theother event is not completed.

For example, if a refresh event occurs, the memory controller generatesa first operation code and first area information (1010), and issues thefirst operation code (1013) even if an operation on the second area isnot completed (NO in 1011) if the first area and the second area aredifferent (No in 1012). If the first area as a refresh event target isthe same as the second area which is being operated (Yes in 1012), theprocessing is kept in standby until the operation of the second area iscompleted (Yes in 1011).

Similarly, once the memory operation event occurs, the memory controllergenerates a second operation code and second area information (1014),and issues the second operation code (1017) as with the above mannereven if an operation on the first area is not completed (NO in 1015) ifthe second area and the first area are different (No in 1016). If thesecond area as a memory operation event target is the same as the firstarea which is being operated (Yes in 1016), the processing is kept instandby until the operation on the first area is completed (Yes in1015).

FIG. 102 is a figure showing a relationship between the backgroundrefresh and horizontal access according to the present embodiment. Inthe memory map 12 the background refresh is executed in banks BA2 andBA3 during the execution of a horizontal access 1020 to banks BA0 andBA1. Similarly, the background refresh is executed in the banks BA0 andBA1 during the execution of a horizontal access 1021 to the banks BA2and BA3. The same applies to horizontal accesses 1022 and 1023. In thismanner, when execution of horizontal accesses is started successively, abank in which no access is generated for a certain period of time can bedetermined, thus the refresh operation can be performed on this bank inwhich no access is made. By performing such control, it is not happenthat a refresh operation command is issued to all banks during thehorizontal access, and so the horizontal access is interrupted.Therefore, in the case in which the image data or othertwo-dimensionally arrayed data is raster scanned and accessed from theupper left to the lower right, dead cycles that are caused by therefresh operation can be eliminated, whereby high-speed raster scanningcan be performed.

FIG. 103 is a figure showing a relationship of the background refresh tohorizontal accesses and rectangular access according to the presentembodiment. There is shown an example in which a rectangular access 1024is generated between the abovementioned horizontal accesses 1020 and1021. In the image processing system constituted by the image memory,memory controller and image processing device, a combination of ahorizontal access and rectangular access is requested against the imagememory. In the rectangular access, an arbitrary address of the memory isaccessed every time when compression/expansion processing is performedon the image data, thus it is difficult to predict which bank isaccessed. In the horizontal access, on the other hand, an access isgenerated only in a specific bank for a certain period of time, and noaccess is generated in the rest of the banks.

Therefore, in the horizontal access 1020, the background refresh commandBREN (a reference numeral 60 in the figure) is inputted along with therefresh bank information SA (a reference numeral 61 in the figure)indicating the refresh target bank. In this example, the horizontalaccess 1020 is generated with respect to the banks BA0, BA1, thus therefresh target banks are BA2 and BA3. In response to the backgroundrefresh command BREN, the control circuit within the memory deviceinstructs the refresh target banks BA2 and BA3 to perform the refreshoperation. In this horizontal access 1020, an active command ACT isinputted along with a bank address BA=0 and a row address RA=0, the pageareas of BA0 and RA0 are activated, then a read command RD is inputtedalong with a bank address BA=0 and a column address CA=0, and the datais read. Similarly, a active command ACT is inputted along with a bankaddress BA=1 and a row address RA=0, the page areas of BA1 and RA0 areactivated, a read command RD is inputted along with a bank address BA=1and a column address CA=0, and the data is read. In the horizontalaccess, these operations are repeated for a certain period of time. Inthe meantime, the refresh operation is repeated in the banks BA2 andBA3.

The operations similar to those described above are carried out in thehorizontal access 1021 as well. Specifically, the background refreshcommand BREN (a reference numeral 65 in the figure) is inputted alongwith BA0, 1 as the refresh bank information SA (a reference numeral 66in the figure), and the refresh operation is performed in the banks BA0,1. In parallel with this refresh operation, and an active command and aread command are repeatedly inputted, whereby the horizontal accessoperation is performed on the banks BA2, 3. During the rectangularaccess 1024, the background refresh operation is not performed.

The abovementioned background refresh command BREN corresponds to thefirst code. Also, the active command ACT and read command RD or writecommand WT (not shown) correspond to the second code.

FIG. 104 is a figure for explaining the number of times and the numberof blocks the background refresh is performed according to the presentembodiment. The background refresh is executed on a bank in which accessis not generated, when access is generated only in a specific bank in acertain period of time or when horizontal access is generated. In thepresent embodiment, in addition to the refresh bank information SAindicating the refresh target bank, the memory device is supplied, fromthe memory controller, with refresh burst length RBL, which indicatesthe number of times the refresh is executed in response to a singlebackground refresh command BREN, and the refresh block count RBC, whichindicates the number of blocks, or precisely, the number of word lines,which are refreshed simultaneously in a signal refresh operation.

Specifically, in the horizontal access a part of banks are repeatedlyaccessed during a certain period of time in accordance with the size ofthe access target image. However, the time period of the horizontalaccess varies, and the horizontal access occurs randomly. Therefore, itis required that the refresh operation be executed on the desired numberof addresses in the refresh target bank during the horizontal access.For example, in the case in which the refresh operation needs to beperformed on an address N during a horizontal access period T, if T÷τ≧Nis satisfied where τ is a cycle time required in a single refreshoperation, the refresh operation may be executed N times on one block(one word line). However if T÷τ≧N is not satisfied, a plurality ofblocks (a plurality of word lines) are subjected to a single refreshoperation simultaneously, whereby the number of N needs to be reducedeffectively. The number of blocks that are subjected to the refreshoperation simultaneously is the refresh block count RBC.

Furthermore, if the size of access target data is larger thanpredetermined size, the horizontal access period is extended by acertain amount. In this case, the number of commands issued can bereduced by repeating the refresh operation a number of times on a singlebackground refresh command BREN. In this case, the number of times therefresh can be executed during the horizontal access period T is T÷τ,which is the refresh burst length RBL. By specifying the refresh burstlength RBL when the horizontal access is started, the refresh cycle isended at the point of time when the horizontal access period T is ended,thus the memory device, immediately thereafter, can issue an activecommand to enter the cycle of the normal memory operation.

Returning to FIG. 104, with regard to the example in which the bankBank0 is constituted by four blocks Block-0 through 3 in the figure,there is shown an example of three combinations of the refresh burstlength RBL and the refresh block count RBC. Each of the block has wordlines WL, bit lines BL, and a group of sense amplifiers S/A that areconnected to the bit lines BL respectively. Each of the four blocksBlock-0 through 3 has the group of sense amplifiers S/A and are capableof performing the refresh operation simultaneously. It should be notedthat the refresh operation is constituted by active operation andpre-charge operation. Also, the normal operation is constituted by theactive operation, read or write operation, and pre-charge operation.

FIG. 104(A) shows an example in which RBL=2 and RBC=1. In response tothe background refresh command BREN, the refresh operation is performedby the word lines WL0 and WL1 of the block Block-0 continuously, and, inresponse to the subsequent command BREN, the refresh operation isperformed by the word lines WL0 and WL1 of the block Block-1continuously. In this case, since RBC=1, the refresh operation isperformed only in one block, thus the amount of current consumed in therefresh operation can be reduced.

FIG. 104(B) shows an example in which RBL=1 and RBC=4. In response tothe background refresh command BREN, the refresh operation is performedby the word lines WL0 of the respective four blocks Block-0 through 3simultaneously. Although only one refresh cycle is executed, the refreshis performed by the four blocks simultaneously, thus four addresses arerefreshed. However, a large amount of current is consumed instantly.

Finally, FIG. 104(C) shows an example in which RBL=2 and RBC=2. Inresponse to the background refresh command BREN, the refresh operationis performed continuously by the word line WL0 and the word line WL1 oftwo blocks Block-0, 1 respectively. Accordingly, the number of rowaddresses to be refreshed is 4. However, since the refresh operation isperformed by two memory blocks simultaneously, the amount of currentconsumed instantly is lower than that in the example of FIG. 104(B).

As described above, in the background refresh of the present embodiment,the refresh bank information SA indicating the refresh target bank, therefresh burst length RBL, and the refresh block count RBC are inputtedalong with the command BREN or the register set command EMRS so as toflexibly respond to the occurrence and period of random horizontalaccesses.

Incidentally, the memory controller can cause the memory device toexecute the background refresh operation a number of times by settingthe refresh burst length RBL, but once the refresh operation is started,it is inconvenient if the number of refresh operations corresponding tothe refresh burst length RBL cannot be changed. Therefore, as will bedescribed hereinafter, in the present embodiment, the refresh burstlength RBL can be increased by addition or reset to obtain new burstlength RBL, or the refresh operation can be stopped. In order toflexibly respond to random horizontal accesses, the background refreshcommand can be issued beforehand by means of a function of adding burstlength RBL. The function of resetting the burst length can be used innew horizontal access is generated. Moreover, the command for stoppingthe refresh operation is effective when the refresh burst length RBLthat has been set once is excessively long.

Further, in the present embodiment, a refresh-all command for executingthe refresh operation on all remaining addresses can be used.Accordingly, the memory area without effective data can be forciblycaused to perform the refresh operation to reset a refresh counter. Thiswill be described hereinafter.

FIG. 105 is a timing chart of the background refresh operation accordingto the present embodiment. FIG. 105(A) shows an example in which thebanks BA0, 1 are caused to perform the refresh operation when thehorizontal access 1020 is made to the banks BA2, 3, wherein the refreshburst length RBL and the refresh block count RBC (a reference numeral1052 in the figure) are issued along with the background refresh commandBREN (a reference numeral 60 in the figure) to the memory device.Thereafter, the active command ACT and the read command RD correspondingto the horizontal access are repeatedly issued.

In FIG. 105(B), on the other hand, before the horizontal access 1020 isstarted, the refresh burst length RBL and the refresh block count RBCare issued (a reference numeral 1053 in the figure) along with anextended mode register set command EMRS (a reference numeral 1051 in thefigure). Accordingly, the memory device sets the RBL and RBC into aninternal mode register. Thereafter, in the horizontal access 1020, therefresh bank information SA is supplied along with the backgroundrefresh command BREN (a reference numeral 1054 in the figure), inresponse to which the memory device performs the refresh operationcorresponding to the registered RBL and RBC. Then, the active commandACT and read command RD corresponding to the horizontal access arerepeatedly issued.

As described above, the refresh burst length RBL and the refresh blockcount RBC may be set each time along with the command BREN, or set intothe mode register beforehand. By setting the refresh burst length RBL,and the refresh block count RBC into the mode register, the refreshburst length RBL and the refresh block count RBC do not have to be seteach time along with the command BREN.

FIG. 106 is a figure for explaining the refresh burst length accordingto the present embodiment. FIG. 106(A) is a timing chart showing thecase in which the refresh is performed once on the auto-refresh commandAREF. FIG. 106(B), on the other hand, is a timing chart showing the casein which the refresh is performed a number of times (RBL) with respectto a single background refresh command BREN, according to the presentembodiment. Both figures show an example in which the refresh isperformed on the banks BA0, 1 during the horizontal access to the banksBA2, 3.

As shown in FIG. 106(A), the refresh bank information (0, 1) is suppliedalong with the auto-refresh command AREF to a bank address terminal BA,the refresh control signal refz is brought to the H level in the memorydevice, and the refresh operation REF is performed. After a lapse oftime tRRD between commands, an active command ACT is issued to BA2 andBA3, in response to which a read command RD is issued to BA2 and BA3,and then a pre-charge command PRE is issued to BA2 and BA3. Thereafter,an auto-refresh command AREF is issued again at the timing of a clocknumber 10, and a refresh is executed on the banks BA0, 1. Accordingly,the refresh operation REF is performed only once in response to a singleauto-refresh command AREF, thus it is necessary to the auto-refreshcommand AREF a number of times.

On the other hand, as shown in FIG. 106(B), in response to thebackground refresh BREN, the refresh operation REF is repeated a numberof times corresponding to the refresh burst length RBL that is setbeforehand. Specifically, the control circuit within the memoryactivates the refresh control signal refz to execute the refreshoperation, and, upon completion thereof, further activates the refreshcontrol signal refz in response to a refresh interval signal refintvalxto execute the refresh operation. In this manner, the refresh operationis repeated a number of times corresponding to the refresh burst lengthRBL. Therefore, it is not necessary to issue a refresh command a numberof times. More specifically, a refresh command is not issued at theclock number 10. Consequently, since the second refresh operation iscompleted earlier by time of 1060 shown in the figure, the refreshoperation cycle becomes substantially short. Therefore, by setting therefresh burst length RBL and automatically executing the refresh anumber of times, the memory controller can issue the command moreefficiently.

FIG. 107 is a figure for explaining the refresh burst length accordingto the present embodiment. FIG. 107(A) is a timing chart showing thecase in which the refresh burst length RBL is specified to perform thebackground refresh, and FIG. 107(B) is a timing chart showing the casein which the background refresh is performed without specifying the RBL.However, both figures show an example in which the refresh operation isperformed a number of times in response to the command BREN.

In the case of FIG. 107(A), in response to a background refresh commandBREN (a reference numeral 1070 in the figure), the memory device repeatsthe refresh operation REF internally by the refresh burst length RBLthat is set beforehand. Therefore, the internal refresh operation iscompleted, and the pre-charge operation, which is performed on the banksBA0, 1, is ended at a clock number 20. Therefore, the memory controllercan issue an active command ACT (a reference numeral 1071 in the figure)to the bank BA0 at a clock number 21 to perform the normal access.

In the case of FIG. 107(B), on the other hand, since the number of timesthe refresh is performed is not specified, the memory device internallyrepeats the refresh operation REF in response to the command BREN (areference numeral 1072 in the figure). The memory controller issues apre-charge command PRE (a reference numeral 1073 in the figure) to thebank BA0 at the clock number 21 in order to stop the repeated refreshoperation. However, a new internal refresh operation REF is started atthe clock number 20, thus this refresh operation cannot be stopped atthe clock number 21 in response to the pre-charge command PRE.Therefore, the memory controller cannot issue an active command ACT (areference numeral 1074 in the figure) until the started refreshoperation is completed, and can eventually issue an active command ACTafter a lapse of time REFC (approximately several 10 ns) since thepre-charge command PRE has been issued, the time being required for therefresh operation. Specifically, if the number of times the refresh isperformed is not specified in advance, the memory controller needs tostop the refresh operation by issuing a pre-charge command. However,since the refresh operation cannot be stopped immediately by issuing apre-charge command for stopping the refresh operation, issuance of anactive command to be issued next becomes delayed.

The invention described in the abovementioned Patent Literature 6, U.S.Patent Application Publication No. US2005/0265104A1, corresponds to FIG.107(B) described above. On the other hand, the present embodimentcorresponds to FIG. 107(A).

Above has described the overview of the background refresh function. Aconfiguration of the memory device for realizing this function isdescribed hereinafter.

[Memory Device with Background Refresh Function]

FIG. 108 is a configuration diagram of the entire memory device havingthe background refresh function. In the figure, a group of inputterminals 93 shows terminals of a clock CLK, command signals/CS, /RAS,/CAS, /WE, 2-bit bank addresses BA<1:0>, and 14-bit addresses A<13:0>respectively, and each of the input signals is inputted to an inputbuffer 94 and latched into a latch circuit 720 in synchronization with aclock CLK. A command decoder 1080 is provided within the commandcontroller 95 shown in FIG. 9, and decodes the command signals/CS, /RAS,/CAS and /WE to output a mode register set pulse signal mrspz, an activepulse signal actpz, a refresh pulse signal refpz, and a pre-charge pulsesignal prepz as internal control signals corresponding to commands EMRS,ACT, BREN, and PRE. The bank addresses BA<1:0> are latched and becomeinternal bank addresses baz<1:0>, based on which a normal bank decoder1081 generates bank selection signals bnkz<0:3>. Moreover, a refreshbank decoder 1082 generates a refresh bank selection signalref_bnkz<0:3> on the basis of the bank address baz<1:0>, a signalinputted from an address terminal, and a set value modez* that is set inthe mode register 96. The mode register 96 sets set values that areinputted from the bank address baz<1:0> and an address az<13:0>, inresponse to the mode register set pulse signal mrspz.

The memory device 86 has four banks 92 in addition to the abovementionedcontrol circuit. Each of the banks has a core 1086 having a memory cellarray, a decoder and a sense amplifier, a core control-circuit 1085 forcontrolling the core, a refresh address counter 1083 for generating arefresh address (row address) REF_RA of each bank, and an address latchcircuit 1084 for latching the address az<13:0> supplied from outside orany of the refresh addresses REF_RA. Although the figure shows only adetailed configuration of the bank Bank0, other banks Banks 1, 2 and 3have the same configuration.

The core control circuit 1085 of each bank activates the internal coreif the bank selection signal bnkz<0:3> is in a selected state, inresponse to the active pulse signal actpz that is generated in responseto the active command ACT. In this case, the address latch circuit 1084latches the address az<13:0> supplied from the outside, supplies theaddress to the decoder within the core 1086. In response the refreshpulse signal refpz generated in response to the background refreshcommand BREN, the core control circuit 1085 activates the internal coreand causes the core to perform the refresh operation, if the refreshbank selection signal ref_bnkz<0:3> is in a selected state. In thiscase, the address latch circuit 1084 latches the refresh address REF_RAof the refresh address counter 1083, supplies the address to the decoderwithin the core.

[Example of Configuration of Banks of Memory Device]

FIG. 109 is a configuration diagram of the banks of the memory devicehaving the background refresh function.

FIG. 109 shows the configurations of four banks shown in FIG. 108. Allof the four banks, Banks 0 through 3, have the refresh address counter1083, address latch circuit 1084, core 1086, and core control circuit1085. The bank selection signal bnkz<0:3> and the refresh bank selectionsignal ref_bnkz<0:3> are inputted to each of the four banks Banks 0through 3, and, when these signals are in the selected state, the corecontrol circuit 1085 brings the core into an active state in response tothe active pulse signal actpz, and further brings the core into theactive state in response to the refresh pulse signal refpz. In thisexample, since each bank has the refresh address counter 1083, refreshcontrol can be performed independently on each bank. Therefore, whileone bank performs the normal memory operation, the refresh control canbe performed on one, two or three banks of the rest of the banks. Therefresh control that is performed independently on each bank isdescribed with reference to FIG. 100.

FIG. 110 is another configuration diagram of the banks of the memorydevice having the background refresh function. In this example, each ofthe Banks 0 through 3 has the core 1086, address latch circuit 1084, andcore control circuit 1085. Furthermore, a refresh address counter 1100is provided in each of two banks, Banks 0 and 1, and the refresh addressREF_RA is supplied to both Banks 0 and 1. Moreover, a refresh addresscounter 1101 is provided in each of two banks, Banks 2 and 3, and therefresh address REF_RA is supplied to both Banks 2 and 3. In thisexample, the refresh control can be performed independently for everytwo banks. Specifically, while Banks 0 and 1 perform the normal memoryoperation, the refresh operation can be performed on Banks 2 and 3simultaneously, and the reverse is also possible. Of course, the fourbanks can be subjected to the refresh operation simultaneously.

FIG. 111 is yet another configuration of the banks of the memory device.In this example, the refresh address counter is not provide within thebank, but pointers 1112 indicating word lines to be refreshed areprovided between an address decoder 1111 and word drivers 1113. In thenormal memory operation, the address latch circuit 1100 that is providedin each bank is activated in response to the active pulse signal actpz,and latches the external address az<13:0>. The address decoder 1111within each bank is activated when the bank selection signal bnkz<0:3>is in the selected state, and decodes the address. The word drivers 1113selected by the decoder drives the word lines, and bring a memory cellare 1114 into the active state. Then, an amplifier control circuit 1115activates a sense amplifier 1116 at a predetermined timing.

On the other hand, at the time of the background refresh, a pointer 1112is activated by the refresh pulse signal refpz when the refresh bankselection signal ref_bnkz<0:3> is in the selected state, the word driver1113 corresponding to the pointer in the selected state drives the wordline, and the refresh operation is performed by the memory cell area1114 and the sense amplifier 1116. Once the refresh operation is ended,the pointer 1112 changes the next pointer to the selected state. In thismanner, every time the refresh operation is ended, the group of pointers1112 moves the selected positions successively so that the word lineswithin the memory cell area can be driven sequentially.

In the example shown in FIG. 111, the pointers 1112 for refresh areprovided in all of the four banks respectively, thus the refresh controlcan be performed on the four banks independently.

FIG. 112 is a figure for explaining the background refresh operationaccording to the present embodiment. FIG. 112(A) is a conventionalexample, herein the memory device performs the refresh operation on allof the internal banks once an auto-refresh command AREF is received.This figure shows an example in which the number of times the refresh isperformed is one. In the refresh cycle tREFC the normal memory operationcan not be executed, thus the normal memory operation is performed againupon reception of an active command ACT from a clock number 9.

On the other hand, FIG. 112(B) shows the present embodiment, wherein thememory device starts the refresh operation on the banks BA0 and 1 thatare specified by the bank address BA, in response to the backgroundrefresh command BREN. In parallel with this, the memory device receivesthe active command ACT and read command RD corresponding to the banksBA2 and BA3, and performs read operation. After reception of the readcommand RD, the memory device receives a pre-charge command PRE andcauses the banks BA2 and BA3 to perform pre-charge operation.

It should be noted that in the example shown in FIG. 112(B), the refreshbank information “0, 1” and the refresh burst length “8” are inputtedfrom the bank address terminal BA and an address terminal Addrespectively, simultaneously with the background refresh command BREN.However, as shown in the figure, the refresh bank information “0, 1” maybe inputted from a terminal SA that is specially provided, and therefresh burst length “8” and a refresh block count “1” may be inputtedfrom terminals RBL and RBC respectively.

As shown in FIG. 112, according to the background refresh function ofthe present embodiment, the refresh operation is performed in parallelwith the normal memory operation, thus the normal memory operation isnot interrupted by the refresh operation.

[Refresh Bank Decoder, Core Control Circuit, and Address Latch Circuit]

Next, specific examples of the refresh bank decoder, core controlcircuit and address latch circuit shown in FIGS. 108 through 111 aredescribed. It should be noted that the relationship between bankaddresses BA<1:0> and a bank to be selected is shown hereinafter as apremise.

Bank selected by BA<1>=0 and BA<0>=0 is Bank 0Bank selected by BA<1>=0 and BA<0>=1 is Bank 1Bank selected by BA<1>=1 and BA<0>=0 is Bank 2Bank selected by BA<1>=1 and BA<0>=1 is Bank 3

FIG. 113 is a figure showing circuits of first and second refresh bankdecoders. A first example of a refresh bank decoder 1082(1) shown inFIG. 113(A) is applied when the memory device performs the refreshoperation for every two banks, and control is performed so as to selectBanks 0, 1 or Banks 2, 3 on the basis of the logic of the bank addressterminal BA<1> when a background refresh command BREN is inputted.Therefore, the logic of the bank address terminal BA<1> is valid (V:Valid), while the logic of the bank address terminal BA<0> is invalid(Don't care). Specifically, if the bank address terminal BA<1>=H, therefresh bank selection signal ref_bnkz<2, 3>=H, thus Banks 2, 3 areselected. If the bank address terminal BA<1>=L, the refresh bankselection signal ref_bnkz<0, 1>=H, thus Banks 0, 1 are selected.

A second example of a refresh bank decoder 1082(2) shown in FIG. 113(B)is applied when the memory device performs the refresh operation forevery two banks, and control is performed so as to select Banks 0, 2 orBanks 1, 3 on the basis of the logic of the bank address terminal BA<0>when a background refresh command BREN is inputted. Therefore, the logicof the bank address terminal BA<1> is invalid (Don't care). The specificoperation is the same as the one of the first example.

In the case in which a combination of banks configuring one line in thehorizontal direction is Bank 0, 1 (or Bank 2, 3), it is preferred thatthe first example be used for the background refresh that is performedat the time of horizontal access. On the other hand, in the case inwhich a combination of banks configuring one line in the horizontaldirection is Bank 0, 2 (or Bank 1, 3), it is preferred that the secondexample be used as the background refresh. The combination of banks inthe horizontal direction depends on the memory mapping of the memorysystem that uses the memory. Therefore, the memory device needs to havethe refresh bank decoder of the first or second example, depending onthe memory mapping.

FIG. 114 is a figure showing a circuit of a third refresh bank decoder.The example of the third refresh bank decoder 1082 (3) is obtained bycombining the first and second examples. The third refresh bank decoder1082(3) has four selectors SEL for selecting either a decode signal on abank address baz<0> side or a decode signal on baz<1> side in accordancewith the set value modez that is set in the mode register. As shown inthe logical value table in the figure, if modez=1, the bank addressbaz<1> becomes valid (V: Valid), whereby the decode signal on baz<1>side is selected in a combination of the refresh bank selection signalsref_bnkz<0, 1> and ref_bnkz<2, 3>. On the other hand, if modez=0, thebank address baz<0> becomes valid (V: Valid), whereby the decode signalon baz<0> side is selected in a combination of the refresh bankselection signals ref_bnkz<0, 2> and ref_bnkz<1, 3>. Therefore, bysetting the set value modez in the mode register in advance inaccordance with the memory mapping, any types of memory mapping can beresponded.

FIG. 115 is a figure showing a circuit of a fourth refresh bank decoder.In the fourth refresh bank decoder 1082(4), a bank selecting mode isswitched by 2-bit set value modez<1:0> that is set in the mode register.The four types of bank selecting modes are as follows, as shown in thetable of the figure.

(1) When modez<1:0>=1, 1, one bank that is specified by the bank addressterminals BA<1> and BA<0> is selected. Specifically, only one bank isselected from the four banks.(2) When modez<1:0>=1, 0, a combination of two banks, i.e. Banks 0, 1 orBanks 2, 3 that are selected by the bank address terminal BA<1>, isselected.(3) When modez<1:0>=0, 1, a combination of two banks, i.e. Banks 0, 2 orBanks 1, 3 that are selected by the bank address terminal BA<0>, isselected.(4) When modez<1:0>=0, 0, all of the refresh bank selection signalsref_bnkz<0:3> enter the selected stated. Therefore, once the refreshcommand BREN is inputted, the refresh is executed in the four banks.

In the refresh bank decoder 1082(4), two NAND gates to which the bankaddress baz<0> is inputted are activated when modez<0>=1, pre-decodesignals baOx, z become 1 or 0, and banks are selected in a combinationof the refresh bank selection signals ref_bnkz<0, 2>, <1, 3>. On theother hand, two NAND gates to which the bank address baz<1> is inputtedare activated when modez<1>=1, a pre-decode signals ba1 x, z become 1 or0, and banks are selected in a combination of the refresh selectionsignal ref_bnkz<0, 1>, <2, 3>.

In the case of this example, in the system that has the combination ofBanks 0, 1 (Banks 2, 3) configuring the one line in the horizontaldirections, the mode register set value may be set to modez<1:0>=1, 0.Also, in the system that has the combination of Banks 0, 2 (Banks 1, 3)configuring the one line in the horizontal direction, the mode registerset value may be set to modez<1:0>=0, 1. Furthermore, in the system inwhich the refresh is performed in units of banks, modez<1:0>=1, 1 may beset, and in the system in which the refresh is performed on all bankssimultaneously as in the conventional manner, modez<1:0>=0, 0 may beset.

FIG. 116 is a figure showing a circuit of a fifth refresh bank decoder.The fifth refresh bank decoder 1082(5) can switch the bank selectingmode (1 bank, 2 banks, 2 banks or 4 banks) by means of a 2-bit addressterminal A<1:0> that is supplied simultaneously with the command BREN.Specifically, in this example, the set value that is inputted from the2-bit address terminal A<1:0> is used in place of the mode register setvalue modez<1:0> of the fourth example shown in FIG. 115. Switching ofthe bank selecting mode is the same as that of FIG. 115. According tothe fifth example, the combination of the refresh bank selections can bechanged every time the command BREN is issued. Therefore, even in thecase of the rectangular mode, the combination of the refresh target bankselections can be changed to perform the refresh in the background.

FIG. 117 is a figure showing a circuit of a sixth refresh bank decoder.The sixth refresh bank decoder 1082(6) can use the bank address terminalBA<1>, BA<0> when the refresh command BREN is inputted, to specify acombination of two banks on which a refresh is performed simultaneously.Switching of a combination of two banks is the same as the third exampleshown in FIG. 114, but the combination switching of the fifth examplecan be performed without using the mode register set value, but usingonly the logics of the bank address terminals BA<1>, BA<0> that areinputted along with the command.

The refresh bank decoder 1082(6) inputs the bank selection signalsbnkz<3:0> that are generated from the bank addresses BA<1:0> by thenormal bank decoder, and then generate refresh bank selection signalsref_bnkz<0:3>

First of all, as shown in a memory map 1170, in the system in which thecombination of the banks configuring one line in the horizontaldirection is Banks 0, 1 (or Bank 2, 3), a bank selection signal bnkz<0>is selected if BA<1>=0 and BA<0>=0 (bankz<0>=High, and the rest is Low),and Bank 0 and Bank 1 are selected. If BA<1>=1 and BA<0>=1, a bankselection signal bnkz<3> is selected (bankz<3>=High, the rest is Low),and Bank 2 and Bank 3 are selected.

On the other hand, as shown in a memory map 1171, in the system in whichthe combination of the banks configuring one line in the horizontaldirection is Banks 0, 2 (or Bank 1, 3), a bank selection signal bnkz<1>is selected if BA<1>=0 and BA<0>=1, and Bank 1 and Bank 3 are selected.If BA<1>=1 and BA<0>=0, a bank selection signal bnkz<2> is selected, andBank 0 and Bank 2 are selected.

FIG. 118 is a figure showing a circuit of a seventh refresh bankdecoder. The seventh refresh bank decoder 1082(7) selects one refreshtarget bank in response to a 4-bit address terminal A<3:0> that isinputted along with the command BREN. For example, an address terminalA<0> is associated with Bank 0, an address terminal A<1> is associatedwith Bank 1, an address terminal A<2> is associated with Bank 2, and anaddress A<3> terminal is associated with Bank 3. Then, when inputting abackground refresh command,

(1) Bank 0 and Bank 1 are selected if A<3>=0, A<2>=0, A<1>=1 and A<0>=1,(2) Bank 2 and Bank 3 are selected if A<3>=1, A<2>=1, A<1>=0 and A<0>=0,(3) Bank 0 and Bank 2 are selected if A<3>=0, A<2>=1, A<1>=0 and A<0>=1,(4) Bank 1 and Bank 3 are selected if A<3>=1, A<2>=0, A<1>=1 and A<0>=0,and(5) Bank 0, Bank 1, Bank 2 and Bank 3 are all selected if A<3>=1,A<2>=1, A<1>=1 and A<0>=1.(6) If any of A<3:0> is 1, one corresponding bank is selected. In thiscase, the bank address terminal BA<1:0> or the rest of the addressterminals A<13:4> are ignored.

FIG. 119 is a configuration diagram of the core control circuit. Thecore control circuit is provided in each bank as shown in FIG. 108. Inthe illustrated example, the core control circuit performs a refreshoperation only once in response to a refresh command. A control circuitfor controlling a refresh operation performed a number of timescorresponding to the refresh burst length RBL of the present embodimentwill be described hereinafter.

First of all, this core control circuit 1085 has a timing controlcircuit 1190 that generates various timing signals in response to anactive pulse signal actpz, refresh pulse signal refpz, and pre-chargepulse signal prepz, and a refresh control circuit 1191 that controls arefresh in response to the refresh pulse signal refpz. An RS flip-flopFF1 constituted by two NAND gates latches an active state, and an RSflip-flop FF3 latches a refresh state. A set input 1192 and a resetinput 1193 are inputted to the RS flip-flop FF1. Furthermore, a setinput 1194 and a reset input 1195 are inputted to the RS flip-flop FF3.

In the figure, an active state signal rasz shows an active state at Hlevel, and also shows a pre-charge state at L level. An equalizingsignal eqlonz equalizes a pair of bit lines of the memory cell array atthe H level, and cancels the equalization at the L level. A word lineactivation signal wlonz activates a word line at the H level, anddeactivates the word line at the L level. A sense amplifier activationsignal saonz activates a sense amplifier at the H level, and deactivatesthe sense amplifier at the L level. The active pulse signal actpz isbrought to the H level by the command decoder in response to an activecommand ACT. The refresh pulse signal refpz is brought to the H levelwhen a refresh command is inputted. The pre-charge pulse signal prepz isbrought to the H level when a pre-charge command PRE is inputted. A bankselection signal bnkz<#> is an output signal of the normal bank decoderand specifies a bank that executes an active or pre-charge operationwhen Bnkz<#> is brought to the H level. A reference numeral “#” is thenumber of a bank. The refresh bank selection signal ref_bnkz<#> is anoutput signal of the refresh bank decoder, and is used to specify a bankthat executes a refresh operation when ref_bnkz<#> is brought to the Hlevel.

FIG. 120 is a timing chart showing an operation of the core controlcircuit. A command decoder that is not shown generates a refresh pulsesignal refpz in response to an auto-refresh command AREF at a clocknumber 0, whereby the RS flip-flops FF1 and FF3 of the bank specified bythe ref_bnkz are set. As a result, the active state signal rasz isbrought to H level, the equalizing signal eqlonz is brought to the Llevel, and the word line activation signal wlonz is brought to H levelafter a lapse of a delay time of a delay circuit DELAY-2. In response tothis, a word line that is selected by a row address is driven. Next, thesense amplifier activation signal saonz is brought to H level after alapse of a delay time of a delay circuit DELAY-3, whereby the senseamplifier is activated and rewriting is performed.

On the other hand, in the state in which the RS flip-flop FF3 is set, arefresh active state signal ref_rasz is also brought to H level. Therefresh pre-charge pulse ref_prepz is brought to the H level from arising edge of the sense amplifier activation signal saonz by an ANDgate 1196 after a lapse of a delay time of a delay circuit DELAY-4, andthe RS flip-flops FF3 and FF1 are reset. By resetting the RS flip-flopFF1, the active state signal rasz is brought to the L level, the wordline activation signal wlonz is also brought to the L level, and theword line is brought to the L level. Then, the equalizing signal eqlonzis brought to the H level after a lapse of a delay time of DELAY-1, thepair of bit lines of the memory cell is then equalized, and thepre-charge of the memory cell array is completed. As a result, one cycleof pre-charge operation is ended.

It should be noted that in the normal operation, once the active pulsesignal actpz corresponding to the active command ACT received at theclock number 9 is brought to the H level, the RS flip-flop FF1 is set,the equalizing signal eqlonz is brought to the L level, the signalsrasz, wlonz and saonz are brought to the H level sequentially, and thememory cell array is activated. Then, once the pre-charge pulse prepzcorresponding to the pre-charge command PRE is brought to the H level,the RS flip-flop FF1 is reset, the signals rasz, wlonz and saonz arebrought to the L level sequentially, the equalizing signal eqlonz isthen brought to the H level, and the memory cell array is pre-charged.This is one cycle of normal operation. At the time of the normaloperation, the refresh control circuit 1191 is not operated.

As described above, the refresh operation is constituted by the activeoperation and the pre-charge operation, while the normal operation isconstituted by the active operation, the read or write operation, andthe pre-charge operation. It should be noted that the illustration of aread command or a write command is omitted in FIG. 120. In a refreshburst operation described hereinafter, abovementioned one cycle ofpre-charge operation is repeated a number of times corresponding to therefresh burst length.

FIG. 121 is a figure showing a configuration and an operation of theaddress latch circuit. The address latch circuit 1084 is provided ineach bank as shown in FIG. 108, and outputs row addresses RA<13:0> tothe memory core. Therefore, thirteen address latch circuits 1084 shownin the figure are provided in parallel. If the bank selection signalbnkz<#> is in the H level, a switch 1201 is conducted, and the addresslatch circuit latches address signals az<13:0> sent from the outside ina latch circuit 1200 in response to an active pulse signal actpz. On theother hand, if the refresh bank selection signal ref_bnkz<#> is in the Hlevel, a switch 1202 is conducted, and the address latch circuit latchesrefresh addresses REF_RA<13:0> of the refresh address counter 1083 inthe latch circuit 1200 in response to a refresh pulse signal refpz.

Further, as shown in the timing chart of FIG. 121, a refresh row addressstrobe pulse signal Ref_ra_strbpz is generated in response to therefresh pulse signal refpz, in response to which the refresh addresscounter 1083 increments the addresses. The incremented refresh addressesREF_RA<13:0> are latched in the latch circuit 1200 in response to thesubsequent refresh pulse signal refpz.

[Refresh Burst Control]

Next, characteristic refresh burst control of the background refreshoperation of the present embodiment is described. In the refresh burstcontrol, the memory device repeatedly performs a refresh operation anumber of times corresponding to the refresh burst length in response toa single background refresh command. Accordingly, as shown in FIG. 106,the number of is suances of the command can be reduced, and the accessefficiency can be enhanced.

FIG. 122 is a timing chart showing a refresh burst operation. In thisexample, in an upper right memory map 12 shown in the figure, the secondrow is accessed horizontally while performing a refresh operation on thefirst row. Refresh bank information SA=0, 1 and refresh burst lengthRBL=4 are supplied from the memory controller to the memory device alongwith a background refresh command BREN at the clock number 0. Moreover,although the refresh block count RBC is also supplied, but this isomitted in this example. As shown in FIG. 105, the refresh bankinformation SA and the refresh burst length RBL are set in the moderegister by means of the mode register set command, or supplied alongwith a refresh command BREN. External terminals to which these items aresupplied are, for example, a bank address terminal, address terminal,special terminal, and the like. A specific example is describedhereinafter.

Once the background refresh command BREN is received at the clock number0, the memory device repeatedly executes refresh operation four times onBanks 0, 1. Furthermore, the memory controller issues an active commandACT to Banks 2, 3 at clock numbers 2, 4, issues a read command RD atclock numbers 5, 7, and further issues a pre-charge command PRE at clocknumbers 8, 9. Similarly, an active command ACT is issued to Banks 2, 3at clock numbers 11, 13, and a read command RD and a pre-charge commandPRE are also issued. In response to this, the memory device executes anactive operation on Banks 2, 3. The active operation performed on Banks2, 3 is executed in parallel with the refresh operation performed onBanks 0, 1.

By specifying the refresh burst length RBL, the four refresh operationsare completed at a clock number 16, and an active command ACT can beissued to Banks 0, 1 immediately after a clock 19.

FIG. 123 is a configuration diagram of the core control circuit thatcontrols the refresh burst operation. By referring to FIG. 119 and FIG.120, this core control circuit becomes clearer. The core control circuit1085 has, in addition to the timing control circuit 1190 and refreshcontrol circuit 1191 shown in FIG. 119, a refresh burst length register1231 in which the refresh burst length RBL is set, a refresh burstlength counter 1230 for counting the number of refresh operations, and arefresh burst end detection circuit 1232 that detects the end of arefresh burst operation by comparing the outputs of the refresh burstlength register 1231 and the refresh burst length counter 1230. The corecontrol circuit 1085 shown in FIG. 123 is an example in which therefresh burst length RBL (four bits: 1 through 16 times) is inputtedalongwith a background refresh command BREN into address terminalsA<7:4> (corresponding to FIG. 105(A)).

As shown in a table 1231T in the figure, refresh burst lengths RBL=1through 16 corresponding to 4-bit information inputted from addressterminals az<7:4> are set in the refresh burst length register 1231, therefresh burst lengths being shown in the table 1231T. This setting isperformed when the refresh pulse signal refpz and refresh bank selectionsignal ref_bnkz<#> that are generated in response to the backgroundrefresh command BREN are equal to H.

The refresh burst length counter 1230 is set when refresh pulse signalrefpz=H and refresh bank selection signal ref_bnkz<#>=H. Every time onecycle of refresh operation is ended, the refresh control circuit 1191outputs an internal refresh pulse signal int_refpz (=H) for directingthe next refresh operation, in response to which the refresh burstlength counter 1230 increments a count value. Then, when the count valueof the counter 1230 matches the burst lengths RBL that are set in therefresh burst length register 1231, the refresh burst end detectioncircuit 1232 outputs a refresh burst end signal rb_endz (=H). Inresponse to this, the refresh control circuit 1191 resets the RSflip-flop circuit that latches a refresh state, and stops outputting thesubsequent internal refresh pulse signal int_refpz and refreshpre-charge pulse signal ref_prepz.

FIG. 124 is another configuration diagram of the core control circuitthat controls the refresh burst operation. This core control circuit1085 is an example in which the refresh burst length RBL that areinputted to the address terminals az<7:4> along with a mode register setcommand EMRS are set in the mode register 96 (corresponding to FIG.105(B)). In response to a mode register set pulse mrspz, 4-bit data thatis inputted to the address terminals az<7:4> is set as the refresh burstlength <the table 1231T shown in FIG. 123), and information on a refreshtarget bank to be inputted to the bank address terminals baz<1:0> isalso set. Furthermore, the refresh block count RBC may also be set.

The refresh burst end detection circuit 1232 inputs, from the moderegister 96, signals modez<7:4> indicating the refresh burst length, andcompares these signals with the count value of the refresh burst lengthcounter 1230. The other configurations are the same as those shown inFIG. 123.

FIG. 125 shows a detailed circuit diagram of the timing control circuit1190 and of the refresh control circuit 1191 within the core controlcircuit. The configurations shown by the arrows 1250 through 1254 in thefigure are added to the configuration shown in FIG. 119. Specifically,an RS flip-flop FF2 that latches a refresh state is set in response to arefresh pulse signal refpz generated by a refresh command BREN, so thata refresh state signal ref_statez shown by the arrow 1250 is set to theH level. This refresh state signal ref_statez is held in the H duringthe refresh burst operation.

In order to control the repetition of the refresh operation, the refreshcontrol circuit 1191 brings the internal refresh pulse signal int_refpz(arrows 1251, 1252) to the H level (pulse width of DELAY-0) after alapse of a delay time of DELAY-5 once the equalizing signal eqlonz isbrought to the H level at the end of the refresh cycle. This internalrefresh pulse signal int_refpz sets the RS flip-flop FF1 (arrow 1253),and directs the start of the next refresh cycle. This internal refreshpulse signal int_refpz increments the refresh counter as describedabove.

Then, in order to stop the refresh operation, in the refresh controlcircuit 1191, when the refresh burst end signal rb_endz (arrow 1254) isbrought to the H level when the refresh cycle corresponding to the burstlength is ended, and when the refresh pre-charge pulse signal ref_prepzis brought to the H level when the refresh operation cycle is ended, theRS flip-flop FF2 is reset by the reset input 1195, and the refresh statesignal ref_statez is reset to L. As a result, the output of an AND gate1197 is fixed to the L level, and the internal refresh pulse signalint_refpz that directs the start of the next refresh cycle is no longeroutputted.

FIG. 126 shows another detailed circuit diagram of the timing controlcircuit 1190 and of the refresh control circuit 1191 within the corecontrol circuit. The refresh control circuit 1191 of this core controlcircuit is provided with, in place of the AND gate 1197 or delay circuitDELAY-5 shown in FIG. 125, an oscillator 1260 that is activated by the Hlevel of the refresh state signal ref_statez. The oscillator 1260 isoscillated at a frequency that is substantially same as that of arefresh cycle, and constantly outputs the internal refresh pulse signalint_refpz for instructing the start of the next refresh cycle. When therefresh burst end signal rb_endz is brought to the H level and therefresh pre-charge pulse signal ref_prepz is brought to the H level atthe end of one cycle of refresh operation, the RS flip-flop FF2 isreset, the refresh state signal ref_statez is reset to L, and theoscillator 1260 is stopped. The other configurations are the same asthose shown in FIG. 124.

The detailed operations of the core control circuit shown in FIGS. 125and 126 are described with reference to FIG. 129 after explaining FIGS.127 and 128.

FIG. 127 is a configuration diagram showing the refresh burst lengthcounter 1230, refresh burst length register 1231, and refresh burst enddetection circuit 1232. This figure is a specific example of FIG. 123and also a specific example without the register shown in FIG. 124. Thecounter within the refresh burst length counter 1230 is reset to “0” inresponse to a refresh pulse signal refpz, and is incremented in responseto an internal refresh pulse signal int_refpz for directing the start ofa refresh cycle. Counter values rblcz<3:0> are outputted to the refreshburst end detection circuit 1232.

The refresh burst length register latches the signals of the addressterminals az<7:4> in response to the refresh pulse signal refpz, andoutputs the latched rblrz<3:0> indicating the refresh burst length tothe refresh burst end detection circuit 1232.

The refresh burst end detection circuit 1232 compares the counter valuesrblcz<3:0> with the refresh burst lengths rblrz<3:0>, and, when bothmatch, outputs a refresh burst end signal rb_endz. The subsequentrefresh operation is stopped by this refresh burst end signal rb_endz.

FIG. 128 is a configuration diagram of the address latch circuit. Inaddition to the configuration shown in FIG. 121, there is aconfiguration in which the address latch circuit 1084 latches therefresh addresses REF_RA<13:0>, which are the outputs of the refreshaddress counter 1083, into the latch circuit 1200 via the switch 1202 inresponse to the internal refresh pulse signal int_refpz shown by thearrow 1280. Specifically, in the refresh burst operation, in order torepeat the refresh cycle, the internal refresh pulse signal int_refpz(=H) is repeatedly outputted. Therefore, in response to this, theaddress latch circuit 1084 needs to latch a new refresh address from therefresh address counter 1083, and increment the same counter.

FIG. 129 is a timing chart of the refresh burst operation. The refreshburst operation that is performed by the core control circuit shown inFIGS. 125 through 128 is explained with reference to FIG. 129 and FIG.120. First, the refresh burst operation is started in response to abackground refresh command BREN. In this example as well, the refreshtarget banks, Banks 0, 1, and the refresh burst length RBL=4 arespecified.

A refresh pulse signal refpz is outputted by the refresh command BREN,in response to which the values of the address terminals A<7> throughA<4> are incorporated into the refresh burst length registers 1231 ofthe refresh target banks, Banks 0 and 1. The rblrz<3:0>=0011b in thefigure is an example in which the burst length RBL=4. At the same time,the counter values of the refresh burst length counters 1230 of theBanks 0 and 1 are reset to rblcz<3:0>=0000b. Moreover, the refresh statesignal ref_statez is set to the H level by the RS flip-flop FF2 withinthe refresh controller circuit 1191.

At this moment, the RS flip-flop FF1 within the timing control circuit1190 is also set, the active state signal rasz=High is set, and therefresh cycle operation is started. At the same time, the timing controlcircuit 1190 sets the equalizing signal eqlonz to Low, the word lineactivation signal wlonz to High, and the sense amplifier activationsignal saonz to the H level as with FIG. 120 (not shown). Accordingly,Banks 0 and 1 enter the active state, and the data of the cells arerewritten.

After a lapse of the delay time DELAY-4 since the sense amplifieractivation signal saonz has been inputted, the refresh pre-charge signalref_prepz is outputted by the AND gate 1196, the RS flip-flop FF1 isreset, the active state signal rasz is set to Low, the equalizing signaleqlonz is set to High, and the pre-charge operation is started. At thismoment, the value of the refresh burst length register 1231 is differentfrom the value of the refresh burst length counter 1230(rblrz<3:0>≠rblcz<3:0>), thus the refresh end signal rb_endz remainsLow.

The refresh control circuit 1191 outputs the internal refresh pulsesignal int_refpz via the AND gate 1197 after lapse of the delay timeDELAY-5 since the equalizing signal eqlonz=High has been set, sets theRS flip-flop FF1, and starts the subsequent refresh operation. At thismoment, the value of the refresh burst length counter is counted up tobecome 0001b. Moreover, the address latch circuit 1084 (FIG. 128)latches the count value of the refresh address counter 1083. Thereafter,the similar refresh operation is repeated.

Once the third internal refresh pulse signal int_refpz is outputted, andthe fourth refresh operation is started, the value of the refresh burstlength counter is counted up to become rblcz<3:0>=0011b. At this moment,the value of the refresh burst length register rblrz<3:0> and the valueof the refresh burst length counter rblcz<3:0> are equal to each other(rblrz<3:0>=rblcz<3:0>=0011b), and the refresh burst end detectioncircuit 1232 sets the refresh burst end signal rb_endz=High. Once thefourth refresh operation is ended, the pre-charge signal ref_prepz isoutputted and the active state signal rasz becomes Low. However, therefresh end signal rb_endz=High, thus the RS flip-flop FF2 is reset bythe reset input 1195, as a result of which the refresh state signalref_statez transits to a Low state. When the equalizing signal eqlonz isset to High as the pre-charge operation is performed, the internalrefresh signal int_refpz for starting the subsequent refresh operationis not outputted according to ref_statez=Low, thus the four refreshburst operations are ended.

In the example shown in FIG. 126 as well, the internal refresh signalint_refpz is outputted by the oscillator 1260. However, when the fourthrefresh operation is started and the refresh state signal ref_statez isreset to L, the oscillator 1260 is stopped, and thereafter the internalrefresh signal int_refpz is not outputted. As a result, the refreshoperation is stopped at the fourth time.

[Refresh Burst Stop Control]

The refresh burst function inputs the background refresh command onceand repeats the fresh cycles by the specified burst length, thus thenumber of inputs of the command can be reduced and the access efficiencycan be enhanced. However, if the burst length is longer, and access isnot allowed to the bank until the background refresh operation that hasbeen started once is ended, the flexibility of the memory control islost. For this reason, the memory device of the present embodiment has arefresh burst stop function.

FIG. 130 is a figure showing an overview of refresh burst stopoperation. The memory device inputs a background refresh command BREN atthe clock number 0, and starts the refresh operation on the banks BNK 0,1 four times=burst length RBL. However, once the memory device inputs astop command STOP during the third refresh cycle, the subsequent refreshcycle is not started after the refresh cycle in progress is ended. Sincethe refresh cycle in progress cannot be stopped, the stop operation thatis performed by means of the stop command STOP means that a new refreshcycle is not started.

The stop command STOP is specified by, for example, a refresh command(e.g., /CS=L, /RAS=L, /CAS=L, /WE=H) and a signal of an address terminalthat is obtained at the time of command input. Specifically, the stopcommand has the same command signal as the refresh command and isdistinguished by the address terminal signal. Alternatively, apre-charge command (e.g., /CS=L, /RAS=L, /CAS=H, /WE=L) is used as thestop command STOP.

FIG. 131 is a configuration diagram of the core control circuit havingthe refresh burst stop function. The refresh control circuit 1191 of thecore control circuit shown in FIGS. 123 and 124 is constituted by arefresh state control circuit 1191B and the refresh state controlcircuit 1191. The command decoder 1080 outputs the refresh pulse signalrefpz in response to the background refresh command, and a refresh stoppulse signal ref_stoppz in response to the stop command.

The refresh state control circuit 1191B sets the refresh state signalref_statez to the H level in response to the refresh pulse signal refpz,and resets the refresh state signal ref_statez to the L level inresponse to the refresh stop pulse signal ref_stoppz. By means of thisrefresh state signal ref_statez, the start and stop of refresh performedby the refresh control circuit 1191 are controlled. Also, the refreshcontrol circuit 1191 ends the refresh operation as described above whena refresh cycle is ended by the refresh burst end signal rb_endzindicating the end of the refresh cycle, the number of the refreshcycles corresponding to the burst length.

FIG. 132 shows a circuit diagram of the refresh state control circuit.FIG. 132(A) shows an example in which the stop command is provided bythe background refresh command BREN and the address terminal signal.FIG. 132(B) shows an example in which the pre-charge command is providedas the stop command. The RS flip-flop FF2 that is incorporated thereincorresponds to the RS flip-flop FF2 shown in FIGS. 125 and 126, andcontrols the refresh state signal ref_statez indicating either therefresh state or refresh stop state.

In either one of the refresh state control circuits 1191B, the RSflip-flop FF2 is set by the refresh pulse signal refpz=H to obtain therefresh state signal ref_statez=H, and is reset by a NAND gate 1321 toobtain the refresh state signal ref_statez=L in response to a refreshburst end signal rb_ends<#> H and the refresh pre-charge pulse signalref_prepz=H. The above is the normal refresh burst operation.

Then, in FIG. 132(A), the RS flip-flop FF2 is reset via an invertor 1322in response to the refresh stop pulse signal ref_stoppz generated by thestop command, and the refresh state signal ref_statez=L is set. In thiscase, only the RS flip-flop FF2 within the refresh target bank is in aset state (refresh state, ref_statez=H), thus only the RS flip-flop FF2within the refresh target bank is reset in response to the commonrefresh stop pulse signal ref_stoppz=H within the memory device.

On the other hand, in FIG. 132(B), the RS flip-flop FF2 is reset only ina bankselected by the refresh bank selection signal ref_bnkz<#>, inresponse to the pre-charge pulse signal prepz=H generated in response tothe pre-charge command. In the normal operation cycle, the refresh bankselection signal ref_bnkz<#>=L is set, thus the RS flip-flop FF2 is notreset by the pre-charge command.

FIG. 133 shows a circuit diagram of the timing control circuit 1190 andof the refresh control circuit 1191 of the core control circuit.Difference with the circuit diagram of FIG. 125 is that, in addition tothe RS flip-flop FF2 of the refresh state control circuit 1191 shown inFIG. 132, the RS flip-flop FF3 for managing the active state andpre-charge state in a refresh operation is also provided, and this RSflip-flop FF3 generates the refresh active state signal ref_rasz. Then,anAND gate 1332 outputsthe refresh pre-charge pulse signal ref_prepz fordirecting pre-charge during a refresh cycle, on the basis of the refreshactive state signal ref_rasz=H, regardless of the state of the refreshstate signal ref_statez. The operation of this refresh active statesignal ref_rasz is the same as the operation of the active state signalrasz during the refresh.

Moreover, the difference with FIG. 125 is that an arbitrating circuit1334 monitors the timing that comes after a lapse of the delay timeDELAY-5 since the equalizing signal eqlonz=H for directing the start ofpre-charge has been inputted, and the timing of the refresh state signalref_statez=L by means of the stop command or pre-charge command. Whenthe refresh state signal ref_statez=H, the arbitrating circuit 1334outputs an internal refresh pulse signal int_refp=H for directing thestart of a new refresh cycle, and, when the refresh state signalref_statez=L, does not output the internal refresh pulse signalint_refpz=H for directing the start of a new refresh cycle.

FIG. 134 shows another circuit diagram of the timing control circuit1190 and of the refresh control circuit 1191 of the core controlcircuit. In this example, in place of the AND gate 1333 shown in FIG.133, the oscillator 1260 is provided, and this example corresponds tothe example shown in FIG. 126. As with FIG. 126, the oscillator 1260enters an enabled state when the refresh state signal ref_statez=H, andoutputs an internal refresh pulse signal int_refpz=H for directing thestart of the subsequent refresh cycle. The oscillator enters a disabledstate when the refresh state signal ref_statez=L. Then, the arbitratingcircuit 1334 monitors the output of the oscillator and the timing of therefresh state signal ref_statez, causes the oscillator output to passwhile the refresh state signal ref_statez is H, and prohibits thepassage of the oscillator output when the refresh state signalref_statez is L.

FIG. 135 is a timing chart showing an operation of FIG. 133. Theoperations of the timing control circuit 1190 and the refresh controlcircuit 1191 shown in FIG. 133 and FIG. 134 are as follows. The RSflip-flops FF1 and FF3 are set in response to the refresh pulse signalrefpz=H by means of the background refresh command BREN, and the activestate signal rasz and the refresh active state signal ref_rasz arebrought to the H level. In response to this, the word lines and senseamplifiers are drive, and the active operation is performed.

When the active operation is ended, the refresh pre-charge pulse signalref_prepz=H is outputted after the del-ay time DELAY-4 in response tothe sense-amplifier activation signal saonz=H, the RS flip-flops FF1 andFF3 are reset, and the active state signal rasz and the refresh activestate signal ref_rasz are brought to the L level. Accordingly, thepre-charge operation is started. After a lapse of the delay time DELAY-5since the equalizing signal eqlonz for starting the pre-charge operationhas been inputted, the internal refresh pulse signal int_refpz=H fordirecting the start of the subsequent refresh cycle is outputted,whereby the subsequent refresh cycle is started.

Then, the stop command STOP is inputted during the active operation ofthe third refresh cycle. In response to this, the refresh stop pulsesignal Ref_stoppz=H is outputted from the command decoder, and therefresh state control circuit 1191B outputs the refresh state signalref_statez=L. At the timing that indicates the end of the activeoperation in the third refresh cycle, i.e., the timing that comes aftera lapse of the delay time DELAY-4 since the sense amplifier activationsignal saonz=H has been inputted, the AND gate 1332 outputs the refreshpre-charge pulse signal ref_prepz=H for directing the start ofpre-charge, on the basis of the refresh active state signal ref_rasz=H.Accordingly, the pre-charge operation in the third refresh cycle isexecuted reliably.

In response to the refresh pre-charge pulse signal ref_prepz=H, the RSflip-flops FF1 and FF3 are reset, and the equalizing signal eqlonz=H isset, whereby the pre-charge operation is started. Then, at the timingthat comes after a lapse of the delay time DELAY-5, the arbitratingcircuit 1334 does not output the internal refresh pulse signalint_refpz=H for directing the start of the subsequent refresh cycle, onthe basis of the refresh state signal ref_statez=L.

In this manner, according to the core control circuit described above,once the stop command STOP to be inputted at arbitrary timing isgenerated using the refresh state signal ref_statez and the refreshactive state signal ref_rasz, the pre-charge operation of the refreshcycle in progress is ended reliably, and a new re-fresh cycle isprohibited from starting after the stop command STOP is inputted.

FIG. 136 shows a circuit diagram of the command decoder that realizesthe refresh stop function. A node 1361 of the command decoder 1080 isbrought to the H level when /CS=L, /RAS=L, /CAS=L, and /WE=H. Then, anaddress terminal A<8> 1360 is brought to the L level, and the refreshpulse signal refpz is set to H by an AND gate 1363 when az<8>=L, wherebythe refresh operation is started. On the other hand, when the addressterminal A<8> 1360 is in the H level and az<8>=H, the refresh stop pulsesignal ref_stoppz is set to H by an AND gate 1362, whereby the refreshoperation is stopped.

[Countdown Refresh Burst Control]

Next, an embodiment in which the refresh burst control is performedusing a down counter is described. In the example described above, therefresh burst counter is counted up for every refresh cycle, but in thefollowing embodiment each refresh burst counter is counted down forevery refresh cycle, andwhen all count valuesof the refresh burstcounters become 0 the refresh burst operation is ended. Therefore, allof the refresh burst counters are reset to zero in response to the stopcommand inputted during the background refresh operation, whereby stopcontrol can be performed.

By using this down counter, a new background refresh command can beinputted before the refresh burst operation is ended, so that controlfor overwriting the refresh burst counter onto burst length that isspecified by a new command, and control for adding the burst lengthspecified by a new command to the current refresh burst counter can beperformed.

Furthermore, the following embodiment describes that, although therefresh address counter is incremented or decremented in every refreshcycle, control is performed for returning the refresh address counterfrom the existing count value to the initial value by means of arefresh-all command for integrally refreshing all of the remainingrefresh addresses.

FIG. 137 is a configuration diagram of the core control circuit 1085that performs countdown refresh burst control. In this example, thestart and stop of a refresh are controlled by means of the backgroundrefresh command BREN and address terminal A<5>.

As with the circuit diagram of FIG. 131, the core control circuit 1085has the timing control circuit 1190 that generates control signals foran active operation and pre-charge operation performed on the core, andthe refresh control circuit 1191 that performs refresh control in abackground refresh operation. Further, the core control circuit has therefresh burst length register 1231 that sets the refresh burst lengthRBL that is inputted from the address terminals A<3:0> in response tothe refresh pulse signal refpz, and the refresh burst length counter1230 that inputs the refresh burst length RBL in response to the refreshpulse signal refpz, is counted down by a down signal downz, and sets allcount vales to 0 in response to the address terminal A<5> correspondingto the stop command.

A refresh burst operation is started by means of the refresh pulsesignal refpz corresponding to a background refresh command, the downsignal downz is outputted for every refresh cycle, whereby the refreshburst length counter 1230 is down counted, and the internal refreshpulse signal int_refpz for directing the start of the subsequent refreshcycle is outputted. The refresh control circuit 1191 repeats theabove-described refresh cycle operation during a period in which all ofthe count values rblcz<3:0> of the refresh burst length counters are notzero (L level). If the all count values rblcz<3:0> become zero (Llevel), the refresh control circuit 191 does not output the internalrefresh pulse signal int_refpz for directing the start of anew refreshcycle. If the all count values rblcz<3:0> are changed to zero (L level)by the stop command from the address terminal A<5>, the refresh controlcircuit 1191 also does not output the internal refresh pulse signalint_refpz anymore.

The core control circuit 1085 shown in FIG. 137 has a refresh addresscomparison circuit 1370. This refresh address comparison circuit 1370sets the refresh-all signal rblcallz to H in response to the refresh-allcommand REFALL, and monitors the refresh addresses ref_az<13:0> of therefresh address counters 1083. When the refresh address comparisoncircuit 1370 detects that all refresh addresses ref_az<13:0> are H, therefresh address comparison circuit 1370 sets the refresh-all signalrblcallz to L. In response to the refresh-all command REFALL, therefresh pulse signal int_refpz is outputted, whereby a refresh operationis started. During a period where the refresh-all signal rblcallz=Huntil all of the refresh addresses ref_az<13:0> of the refresh addresscounter 1083 become H, the refresh control circuit 1191 continuesoutputting the internal refresh pulse signal int_refpz. Then, when therefresh-all signal rblcallz is brought to L by the refresh addressesref_az<13:0>=all H, the refresh control circuit 1191 stops outputtingthe internal refresh pulse signal int_refpz, whereby the subsequentrefresh cycles are no longer generated. It should be noted that therefresh address counter 1083 counts down the refresh addressesref_az<13:0> in response to the sense amplifier activation signal saonz.The countdown may be performed in response to the internal refresh pulsesignal int_refpz in place of this sense amplifier activation signalsaonz.

FIG. 138 is a truth table showing a relationship between a refresh burstlength set in the refresh burst length register 1231 and the addressterminals A<3:0>. The values of the address terminals A<3:0> are set inthe register 1231 directly as the refresh burst length.

FIG. 139 is a configuration diagram of the core control circuit 1085that performs the countdown refresh burst control. In this circuit therefresh burst length counter 1230 is reset to ALL=0 in response to astop command REFSTOP. The other configurations are the same as those ofthe circuit diagram shown in FIG. 137.

FIG. 140 shows a circuit diagram of the timing control circuit 1190 andof the refresh control circuit 1191 within the core control circuit1085. As in the above explanation, the timing control circuit 1190 hasthe RS flip-flop FF1 that is set in response to the signals, the activepulse signal actpz that is inputted at the time of a normal operation,the refresh pulse signal refpz that is inputted at the time of abackground refresh operation, and the internal refresh pulse signalint_refpz that is inputted during a refresh burst operation. When theflip-flop FF1 is set, the active state signal rasz<#> and the like areoutputted, whereby the core is subjected to an active operation.

Then, the refresh control circuit 1191 sets the refresh interval signalrefitvalx to H after a lapse of a delay time DELAY-6 after the activestate signal rasz<#> is brought to the L level, and outputs the internalrefresh pulse signal int_refpz for directing the start of the subsequentrefresh cycle. Furthermore, the refresh control circuit 1191 outputs thedown signal downz=H of the pulse width of a delay time DELAY-7 inresponse to a word line drive signal wlonz<#>=H, and counts down thecount value of the refresh burst length counter 1230.

An output of a NAND gate 1400 is brought to the L level when all of therefresh burst length count values rblcz<3:0>=L and when the refresh-allsignal rblcallz=L, whereby the output of the internal refresh pulsesignal int_refpz is prohibited via an AND gate 1401. In the normalstate, the refresh-all signal rblcallz=L, thus when all of the refreshburst length count values rblcz<3:0> become L during the refresh burstoperation, the output of the internal refresh pulse signal int_refpz isprohibited. Moreover, during a period where the refresh-all signalrblcallz corresponding to the refresh-all command is H, the internalrefresh pulse signal int_refpz is outputted regardless of the refreshburst length count values rblcz<3:0>.

It should be noted that the address-terminal A<10> shown in FIG. 140 isa signal for directing a pre-charge operation for all banks that theSDRAM has, and resets the RS flip-flop FF1 to control the pre-chargeoperation. The specific operation of the above-described circuit isdescribed hereinlater.

FIG. 141 and FIG. 142 each shows a circuit diagram of the refresh burstlength register 1231 and of the refresh burst length counter 1230. FIG.141 is an example in which the stop command is inputted by thebackground refresh command BREN and address terminal A<5>, while FIG.142 is an example in which the stop command is inputted by a dedicatedcommand REFSTOP. The other configurations are the same with each other.

The refresh burst length register 1231 incorporates the refresh burstlength from the address terminals A<3:0> into latch circuits 1410, 1412in response to a refresh pulse signal refpz. Gates 1411, 1413 outputsthe latched values directly as the refresh burst length register valuesrblrz<3:0>, since normally a down signal downz and a self refresh modesignal srefz are both in the L level. Furthermore, the refresh burstlength register 1231 sets the register values rblrz<3:0> to 0001 inresponse to the self refresh signal srefz=H that directs theconventional refresh operation of the SDRAM.

The refresh burst length counter 1230 has a down counter 1414 thatincorporates the register value rblrz<3:0> in response to the refreshpulse signal refpz=H, and down counts the register values in response ofthe down signal downz=H. The down counter 1414 resets all rblcz<3:0> toL in response to the refresh pulse signal refpz=H and address terminalA<5>=H corresponding to the stop command (in response to the refreshstop command REFSTOP in the example shown in FIG. 142).

FIG. 143 shows a circuit diagram of the refresh address counter 1083 andof the refresh address comparison circuit 1370. The refresh addresscounter 1083 is a 14-bit counter, and counts down the refresh addressesref_az<13:0> in responseto the refresh bank selection signalref_bnkz<#>=H and the sense amplifier activation signal saonz<#>=H.

The refresh address comparison circuit 1370 has an RS flip-flop FF4 thatis set in response to the refresh-all command REFALL, and a group ofNAND gages 1432 for detecting whether all of the refresh addressesref_az<13:0> are H. In the normal state, the RS flip-flop FF4 is reset,a node 1430 is in the H level, and the refresh-all signal rblcallz is L.Then, the RS flip-flop FF4 is set in response to the refresh-all commandREFALL, whereby the node 1430 is brought to the L level, and therefresh-all signal rblcallz becomes H. During a period where rblcallz=H,the refresh operation is repeated by the refresh control circuit 1191,and the refresh address counter 1083 is down counted every time thesense amplifier activation signal saonz becomes H. When all of therefresh addresses ref_az<13:0> are changed from L to H, the NAND group1432 detects this change, brings the node 1431 to the H level, and setsthe refresh-all signal rblcallz to L. In response to this, the refreshcontrol circuit 1191 stops the refresh operation, and the RS flip-flopFF4 is reset. Accordingly, a refresh-all operation for refreshing all ofthe remaining addresses within the refresh address counter 1083 isended.

FIG. 144 is a timing chart showing the case in which the RBL of thecountdown core control circuit is 3. The refresh pulse signal refpz=H isgenerated in response to the background refresh command BREN, inresponse to which the register 1231 and counter 1230 shown in FIGS. 141and 142 are reset, and the refresh burst length register valuesrblrz<3:0> and the refresh burst length counter values rblcz<3:0> areall set to 0011b. The output of the NAND 1400 of the refresh controlcircuit 1191 shown in FIG. 140 is changed from L to H byrblcz<3:0>=0011b, and the internal refresh pulse signal int_refpz=H isoutputted. Also, the RS flip-flop FF1 of the timing control circuit 1190shown in FIG. 140 is set, the active state signal rasz is brought to theH level, and the refresh control circuit 1191 sets the refresh intervalsignal refitvalx to L by means of an AND gate 1402, whereby the internalrefresh pulse signal int_refpz=L is set.

Then, the core is subjected to the active operation, and the refreshcontrol circuit 1191 outputs the down signal downz=H via an AND gate1430 in response to the sense amplifier activation signal saonz=H. Inresponse to this, the refresh burst length counter 1230 shown in FIGS.141 and 142 counts down the count values rblcz<3:0>. The refresh controlcircuit 1191 sets the refresh interval signal refitvalx to H after alapse of the delay time DELAY-6 since the active state signal rasz hasbeen brought to the L level, and outputs a new internal refresh pulsesignal int_refpz.

Then, once the abovementioned refresh cycle is repeated three times, thecount values rblcz<3:0> of the refresh burst length counter becomes0000b, then the output of the NAND gate 1400 of the refresh controlcircuit 1191 is brought to the L level, and subsequent internal refreshpulse signals int_refpz are not outputted by the AND gate 1401. In thismanner, the refresh operation of the burst length 3 is ended.

FIG. 145 is a timing chart of a refresh stop operation performed by thecountdown core control circuit. In this example, a refresh operation isstopped by the stop command during the refresh operation of the refreshburst length RBL=3. Once a refresh start command is inputted by thebackground refresh command BREN and address terminal A<5>=L, a refreshoperation is started. The starting operation is the same as the oneshown in FIG. 144. Then, when the refresh stop command is inputted bythe background refresh command BREN and address terminal A<5>=H at alock number 7, the refresh burst length counter 1230 (FIG. 141) isreset, and the counter values rblcz<3:0> thereof become 0000b. Inresponse to this, the output of the NAND gate 1400 of the refreshcontrol circuit 1191 is brought to the L level, and subsequent internalrefresh pulse signals int_refp are not outputted. It should be notedthat the pre-charge of the refresh cycle is controlled by the timingcontrol circuit 1190 in the same manner as the control of the normaloperation.

FIG. 146 is a timing chart of the refresh stop operation of thecountdown core control circuit. Unlike FIG. 145, the stop control isperformed by the refresh stop command REFSTOP. The other configurationsare the same as those shown in FIG. 145.

FIG. 147 is a timing chart showing the refresh-all operation of thecountdown core control circuit. REFALL=H is set in response to therefresh-all command REFALL, the RS flip-flop FF4 of the refresh addresscomparison circuit 1370 (FIG. 143) is set, the node 1430 is brought tothe L level, and the refresh-all signal rblcallz=H is set. Accordingly,the output of the NAND gate 1400 of the refresh control circuit 1191(FIG. 140) is brought to the H level, and the internal refresh pulsesignal int_refpz=H is outputted, whereby the refresh cycle is started.

The refresh addresses ref_az<13:0> of the refresh address counters 1083(FIG. 143) are counted down in every refresh cycle. When all of theref_az<13:0> are L (count value 0000h) and all of the ref_az<13:0> are H(count value 3FFFh), the NNAD gate group (FIG. 143) detects such change,whereby the refresh-all signal rblcallz=L is set, the NAND gate 1400 ofthe refresh control circuit 1191 (FIG. 140) is brought to the Llevel,and then the output of the internal refresh pulse signal int_refpz isstopped. Accordingly, the refresh operation performed on each of theremaining refresh addresses is ended, and the count values of therefresh address counters 1081 are all reset to 1.

FIG. 148 is a timing chart showing an operation for resetting therefresh command, the operation being performed by the countdown corecontrol circuit. In this figure, at the first background refresh commandBREN, the refresh burst length RBL=14 (A<3:0>=110b) is set to start arefresh operation, and the refresh burst length counter is counted downin every refresh operation. Then, the refresh burst length RBL=2(A<3:0>=0010b) is further inputted at the second command BREN before therefresh burst length counter values rblcz<3:0> become 0000b, and newrefresh burst length RBL=2 (A<3:0>=0010b) is added to these countervalues rblcz<3:0>=1101b, whereby the counter values rblcz<3:0> become1101b (thirteen times remaining).

In this manner, the function of adding the refresh burst length by meansof a new background refresh command is provided in the refresh burstcontrol, whereby the memory controller can preferentially issue thebackground refresh command in order to perform the background refreshoperation in the future.

FIG. 149 is a timing chart showing an operation for resetting therefresh command, the operation being performed by the countdown corecontrol circuit. In this example, the refresh burst length RBL=2(A<3:0>=0010b) is inputted at the second command BREN, the new refreshburst length RBL=2 (A<3:0>=0010b) is overwritten in place of the countervalues rblcz<3:0> obtained at that moment, and the counter valuesrblcz<3:0> become 0010b (two times remaining).

In this manner, the function of rewriting the refresh burst length bymeans of a new background refresh command is provided in the refreshburst control, whereby the memory controller can cancel the backgroundrefresh operation that has been started once, to start new backgroundrefresh operation. By adding and rewriting the burst length RBL by meansof the new background refresh command as shown in FIGS. 148 and 149,after the refresh operation is started the contents thereof can bechanged freely, and the flexibility of the control of the memorycontroller can be improved.

[Active and Refresh Interlocking Control]

Next, control for interlocking an active operation and a refreshoperation is described. In the embodiment described above, the activecommand ACT in the normal memory operation and the command BREN in thebackground refresh operation are different commands. The memorycontroller issues these commands separately, and thereby causes thememory device to execute the normal memory operation and the backgroundrefresh operation.

In the following embodiment, on the other hand, setting is performed soas to execute the background refresh operation in conjunction with anactive command in the mode register or the like beforehand, whereby thememory device performs a normal active operation in a selected bank anda refresh operation in a refresh target bank in response to the input ofthe active command for the normal memory operation. Such a function isprovided so that the memory controller does not have to issue thebackground refresh command.

FIG. 150 is a timing chart showing the active and refresh interlockingcontrol. At a clock number 2, an active command ACT and a bank addressBA=2 are inputted, in response to which the memory device executes anactive operation in BANK2 and a refresh operation in BANK1. Furthermore,at a clock number 4, an active command ACT and a bank address BA=3 areinputted as shown in the table in the figure, in response to which thememory device executes the active operation in BANK3 and the refreshoperation in BANK0.

Specifically, as shown in the table in the figure, in response to thevalues of the bank addresses BA<1:0> that are inputted along with theactive commands ACT, the memory device executes the refresh operation ina specific bank. More specifically, if the BANK0 is selected by theactive command, the refresh operation is performed in the BANK3, if theBANK1 is selected by the active command, the refresh operation isperformed in the BANK2, if the BANK2 is selected by the active command,the refresh operation is performed in the BANK1, and if the BANK3 isselected by the active command, the refresh operation is performed inthe BANK0. By using such combinations, even in either the memory mapping1170 or 1171 shown in FIG. 117, the active command issued whenhorizontal access is made can be used to perform a background refresh ona bank, which is not a horizontal access target.

In the present embodiment, the background refresh operation is executedonce in response to the active command ACT. Therefore, the refresh burstlength RBL is fixed to 1.

FIG. 151 is a circuit diagram of the refresh bank decoder in the activeand refresh interlocking control. When the mode value modez=H, an ANDgate group 1510 within the refresh bank decoder 1082 outputs a refreshbank selection signal ref_bnkz<#>=H in response to each of the bankselection signals bnkz<#>=H outputted by the normal bank decoder. Therelationship between the bank selected in the normal active operationand the refresh selection bank is as shown in the table of FIG. 150. Onthe other hand, when the mode value modez=L, the AND gate group 1510sets all of the refresh bank selection signals ref_bnkz<3:0> to L andprohibits the refresh operation performed in collaboration.

The mode value modez=H/L is set in an incorporated register beforehandby the mode register set command EMRS. Alternatively, the mode valuemodez=H/L is inputted from a predetermined external terminal. Therefore,according to the example described above, preferably the mode valuemodez=H is set in the case of a horizontal access, and the backgroundrefresh operation is performed in conjunction with the active commandACT. In the case of a rectangular access, preferably the mode valuemodez=L is set, and the background refresh operation is prohibited.

FIG. 152 is a circuit diagram of the core control circuit in the activeand refresh interlocking control. The core control circuit 1085 isprovided in each bank, thus the controls performed in the banks aredistinguished from one another by the bank selection signals bnkz<#> andrefresh bank selection signals ref_bnkz<#>. First, in a selected bank(bnkz<#>=H), the RS flip-flop FF1 of the timing control circuit 1190 isset via a NAND gate 1520 in response to the active pulse signal actpz=H,and the active state signal rasz is brought to the H level, whereby thecore is subjected to the active operation.

In the refresh selection bank (ref_bnkz<#>=H), on the other hand, the RSflip-flop FF1 is set via a NAND gate 1521 in response to the activepulse signal actpz =H, and the active state signal rasz is brought tothe H level, whereby the core is subjected to the active operation. Atthe same time, the RS flip-flop FF3 within the refresh control circuit1191 is also set via a NAND gate 1522 in response to the active pulsesignal actpz=H, and the refresh active state signal ref_rasz is set tothe H level. The refresh operation is started by setting the activestate signal rasz to the H level, and then the RS flip-flop FF1 is resetby the refresh pre-charge pulse signal ref_prepz=H brought in responseto the sense amplifier activation signal saonz=H, whereby the pre-chargeoperation is performed. At the same time, the RS flip-flop FF3 is reset.

FIG. 153 is a circuit diagram of the address latch circuit in the activeand refresh interlocking control. This circuit also is provided in eachbank. In the selected bank (bnkz<#>=H), the address latch circuit 1084latches an external address az<13:0> in the latch circuit 1200 inresponse to the active pulse signal actpz=H. In the refresh selectionbank (ref_bnkz<#>=H), on the other hand, the latch circuit 1200 latchesthe refresh address ref_az<13:0> of the refresh address counter 1083 inresponse to the active pulse signal actpz=H. Moreover, in response to anormal refresh pulse signal refpz=H as well, the latch circuit 1200latches the refresh address ref_az<13:0>. The other configurations arethe same as those shown in FIG. 128.

As described above, in response to the normal active command, the normalactive operation and the background refresh operation are executed inparallel in accordance with a combination of banks that is setbeforehand.

[Control using Refresh Block Count]

Next, control that is performed using the refresh block count RBCaccording to the present embodiment is described. In the backgroundrefresh operation of the present embodiment, in addition to the refreshburst length RBL that defines the number of refresh cycles, the numberof blocks (the number of word lines) RBC that are activatedsimultaneously in a single refresh cycle can be set.

By increasing the refresh block count RBC, a refresh can be executed ona larger number of refresh addresses simultaneously. Therefore, when aperiod in which the background refresh can be performed is short, it isdesired that the refresh block count RBC be large. On the other hand, ifthe refresh block count RBC is increased, the refresh operation isexecuted on a larger number of word lines simultaneously, and the amountof power that is consumed instantly is increased. Therefore, if theperiod in which the background refresh can be performed is long, it isdesired that the refresh block count be small as much as possible. Thus,the memory controller sets the refresh block count RBC to an optimalvalue in accordance with the period in which the background refresh canbe performed and the conditions of the power consumption.

FIG. 154 is a configuration diagram of a bank circuit. As described withreference to FIG. 108, each bank 92 has the refresh address counter1083, the address latch circuit 1084, a memory cell array 1086Mconfiguring the core circuit, and a row decoder 1086D. The memory cellarray 1086M has four blocks, RBLK 0 through 3, that are constituted bymemory cell arrays MCA 0 through 3 and pairs of sense amplifier columnsSA00, 01 through SA30, 31. All of the four blocks RBLK 0 through 3 havethe sense amplifier column SA, and thus are activated simultaneously sothat a refresh operation can be performed. Then, one or both of theupper two bits of the count value REF_A<13:0> of the refresh addresscounter 1083 degenerate (inverted and non-inverted addresses are set tothe H level). Due to this degeneration, the row address RA<13:0> that isinputted to the row decoder 1086D becomes an address that can performany of the operations of activating the four blocks RBLK 0 through 3simultaneously, activating two blocks simultaneously, and activating oneblock.

FIG. 155 is a figure showing control of the memory block within the corecorresponding to the refresh block count. In the case in which therefresh block count RBC=1 (modez<1:0>=00), the word line WL of thememory block RBLK0, which is a refresh target within the core, is drivenin response to the background refresh command BREN, whereby a refreshoperation is performed. In the case in which the refresh block countRBC=2 (modez<1:0>=01), the word lines WL of two memory blocks RBLK0, 2,which are the refresh targets within the core, are driven in response tothe background refresh command BREN, whereby the refresh operation isperformed. In the case in which the refresh block count RBC=4(modez<1:0>=11), the word lines WL of the four memory blocks RBLK 0, 1,2 and 3, which are the refresh targets within the core, are driven inresponse to the background refresh command BREN, whereby the refreshoperation is performed.

FIG. 156 is a circuit diagram of the address latch circuit. As shown ina truth table in the figure, 1, 2 or 4 indicates the number of wordlines that are activated simultaneously by the signals modez <0> though<1> setting the refresh block count RBC set in the mode register.

The address latch circuit 1084 has a latch group 1564 that latches anon-inverted signal and inverted signal of an upper 2-bit address out of14-bit row address, and a latch group 1565 that latches lower 12-bitaddress. The latch group 1564 latches non-inverted signals of externaladdresses az <13> and <12> and inverted signals obtained by inventors1566 and 1567, in response to an active pulse signal actpz. Similarly,the latch group 1564 latches non-inverted signals of refresh addressesREF_A <13> and <12> and inverted signals obtained by invertors 1568 and1569, in response to a refresh pulse signal refpz. However, thenon-inverted signals and inverted signals of the refresh address REF_A<13> and <12> are caused to degenerate to the H level by NAND gates 1560through 1563 in response to signals modez <0> and <1> set in the moderegister. Accordingly, the word lines of a plurality of memory blockscan be driven simultaneously.

FIG. 157 is a circuit diagram of a predecoder circuit within the rowdecoder. This predecoder circuit generates block selection signalsrblkz<3:0> for selecting four memory blocks by means of a combination ofnon-inverted signals raz <12> and <13> and inverted signals rax <12> and<13> of an upper 2-bit row address. An operation performed by thepredecoder circuit is shown in the table in the figure.

The operations shown in FIG. 156 and FIG. 157 are as follows.

First of all, in the case in which RBC=1, modez<0>=modez<1>=0,

raz<13> and REF_A<13> are in-phase, rax<13> and REF_A<13> arereversed-phase, and

raz<12> and REF_A<12> are in-phase, rax<12> and REF_A<12> arereversed-phase.

One of the four Blocks RBLK is selected by the pre-decoder circuit1086D, whereby one word line WL of the selected block is activated.

Next, in the case in which RBC=2, modez<0>=1, modez<1>=0, raz<13> is setto High, rax<13> is also set to High, raz<12> and REF_A<12> arein-phase, and rax<12> and REF_A<12> are reversed-phase. Then, two of thefour Blocks RBLK are selected by the pre-decoder circuit 1086D, wherebytwo word lines WL of the selected blocks are activated.

Finally, in the case in which RBC=4, modez<0>=1, modez<1>=1, raz<13> isset to High, rax<12> is also set to High, raz<13> is set to High, andrax<12> is also set to High. Then, four of the four Blocks RBLK areselected by the pre-decoder circuit 1086D, whereby four word lines WL ofthe selected blocks are activated.

The above is the explanation of the memory device having the backgroundrefresh-function. Next, the memory controller that controls the memorydevice and causes the memory device to perform the background refreshoperation is described.

[Memory Controller Controlling Background Refresh]

In order to cause the memory device to execute the background refreshfunction, the memory controller needs to provide the background refreshcommand BREN, refresh bank information SA, and refresh burst length RBLto the memory device. Furthermore, it is preferred that the memorycontroller provide the refresh block count RBC to the memory device.Hereinafter, the memory controller that controls a background refresh isdescribed.

FIG. 158 is a configuration diagram of a memory system having thebackground refresh function. An image processing device 81 outputs ahorizontal access request or rectangular access request for accessingtwo-dimensionally arrayed image data to the memory controller 82, andthe memory controller performs access control on the memory device 86.The image processing device 81 outputs an access request signal REQ, anaccess type signal ATYP, an image address ADR, an image size signalSIZE, and a read/write signal RWX to the memory controller 82, inresponse to which the memory controller 82 replies with an acknowledgesignal ACK. Further, write data or read data is transferred by means ofa data bus DATA, while asserting a strobe signal STB.

On the basis of the access request and various information sent from theimage processing device 81, the memory controller 82 outputs thebackground refresh command, refresh bank information SA, refresh burstlength RBL, and the refresh block count RBC to the memory device 86 inthe case of a horizontal access, and further outputs an active commandCMD, a bank address BA, a row address RA, a read or write command CMS, abank address BA, and a column address CA that correspond to thehorizontal access, to the memory device 86. Further, the memorycontroller 82 outputs similar signals corresponding to a rectangularaccess to the memory device 86. Then, the memory controller 82 outputswrite data DQ to the memory device 86 in the case of a write access, andinputs read data DQ from the memory device 86 in the case of a readaccess.

FIG. 159 is a figure showing an example of memory mapping. The figureshows a relationship between the various information items that thememory controller 82 receives from the image processing device 81. Thismemory mapping 12 correspond to frame image data constituted by a totalof 2048 pixels in which 64 pixels are arranged in an X direction and 32pixels are arranged in a Y direction. A block constituted by 8×8 pixelsis associated with a page area that is specified by a bank address BAand a row address RA. Each of the pixels has, for example, one byte ofimage data. In the page areas, the odd-numbered rows are associated withbank addresses BA0, BA1, and the even-numbered rows are associated withbank addresses BA2, BA3.

In such memory map 12, an upper left pixel corresponds to an imageaddress of ADR=0x00, POSX, POSY=0, 9. A right end pixel in the first rowcorresponds to an image address of ADR=0x03F, POSX, POSY=0, 63. A leftend pixels in the 32^(nd) row corresponds to an image address ofADR=0x7C0, POSX, POSY=31, 0. In this case, the image address ADR can beexpressed by the position information POSX, POSY of the upper leftpixels in an access area. Specifically, for the 12 bits of imageaddresses ADR[11:0],

POSY[5:0]=ADR[11:6], POSX[5:0]=ADR[5:0].

Therefore, the memory controller 82 can obtain the position informationPOSX and POSY of the upper left pixel of the access area from the imageaddresses ADR received from the image processing device 81. It should benoted that in the example shown in FIG. 159, since there are thirty-twopixels in a vertical direction, the position information POSY[5:0] inthe vertical direction may have 5 bits.

Next, the size in a horizontal direction of the access area, SIZEX, andthe size in a vertical direction, SIZEY, are supplied by the image sizesignal SIZE and access type signal ATYP respectively. Specifically,SIZEX=SIZE and SIZEY=ATYP. In the case of a horizontal access,SIZEY=ATYP=0_(—)0000b is supplied, and in the case of a rectangularaccess, the value of SIZEY=ATYP is any value other than 0. Therefore,the memory controller 82 can discriminate whether an access is ahorizontal access or rectangular access, based on whether the value ofthe access type signal ATYP is 0 or not.

FIG. 160 is a figure showing a front pixel address and the sizeinformation in a horizontal access and a rectangular access. In the caseof the horizontal access (A), the front pixel address and the size areSIZEX=SIZE, SIZEY=ATYP=0, as shown. In the case of the rectangularaccess (B), the front pixel address and the size are SIZEX=SIZE,SIZEY=ATYP, as shown.

Also, on the basis of the memory map 12, the memory controller 82 canobtain the bank address BA and row address RA of the front pixel in theaccess area from the position information POSX, POSY of the upper leftpixel in the access area. The memory controller 82 can discriminatewhether to access a plurality of banks, on the basis of the positioninformation POSX and POSY of the upper left pixel of the access area,and the size information SIZE and ATYP.

Furthermore, the memory controller 82 can obtain the number of pixelsaccessing the memory device, on the basis of the size information SIZEand ATYP, and can further determine that the next memory access requestis not generated for a period of time corresponding to the number ofclock cycles required for transferring at least the data on the numberof pixels to the image processing device. The memory controller 82 canfurther obtain the refresh burst length RBL in a background refresh onthe basis of such period of time, and can also obtain the refresh blockcount RBC.

FIG. 161 is a configuration diagram of the memory controller. Thismemory controller 82 has a horizontal access determination section 1610,a refresh burst length RBL calculator 1611, an active bank numbergenerating section 1612, a background refresh bank number generatingsection 1613, a memory interface 1614, a controller 1615 incorporated inthe memory interface 1614, and the like. These components configure oneof a plurality of sequencers SEQ shown in FIG. 90. Therefore, aplurality of sequencers SEQ shown in FIG. 161 are provide in accordancewith a plurality of access sources.

The horizontal access determination section 1610 uses a first comparatorCMP1 to determine whether the access type signal ATYP indicating thesize in a vertical direction SIZEY is “0” or not. The output of thefirst comparator CMP1 is “1” if ATYP=0. The horizontal accessdetermination section 1610 further uses a second comparator CMP2 todetermine whether the size signal SIZE indicating the size in ahorizontal direction SIZEX exceeds the number of clocks MEMREF in asingle refresh cycle. The output of the second comparator CMP2 is “1” ifSIZE≧MEMREF. Therefore, if the outputs of both comparators are “1”, anAND gate outputs a background refresh enable signal “1”, and requeststhe controller 1615 to issues a background refresh command. The numberof clocks MEMREF described above is set in, for example, a registerwithin a memory controller.

Next, the refresh burst length RBL calculator 1611 calculates therefresh burst length RBL in a background refresh. Specifically, bydividing the size in a horizontal direction SIZE by the number of clocksMEMREF, the possible number of refresh cycles can be obtained. Thisdivision is performed by a bit shift circuit SFT. Then, the refreshburst length RBL is outputted by the address terminals A[7:4] to thememory device as 0 through 15 or 1 through 16, as shown in, for example,FIG. 123 and FIG. 138.

Also, the active bank number generating section 1612 has an adder ADD, athird comparator CMP3, a decoder DEC0, a selector SEL0, and a decoderDEC1. The decoder DEC1 converts an input signal to an output signal withreference to a table. The active bank number generating section 1612obtains a bank address corresponding to an access area, on the basis ofthe size signal.SIZE and image address ADR supplied from the imageprocessing device. This bank address BA[1:0] indicates a bank number tobe outputted along with an active command.

FIG. 163 is a table for explaining the decoder DEC0 and selector SEL0 ofthe active bank number generating section. In the active bank numbergenerating section 1612, the adder ADD adds a lower 3-bit ADR[2:0] of animage address ADR and the size signal SIZE, which is the size in ahorizontal direction. The lower 3-bit ADR[2:0] of the image address isthe lower three bits of the position information POSX=ADR[5:0] on aposition in a horizontal direction of a front pixel, and is theinformation indicating the position of a pixel within a page areacomposed of 8×8 pixels in the memory map 12 shown in FIG. 159. Then, thecomparator CMP3 determines whether the value, which is obtained byadding the size in the horizontal direction SIZE to the lower 3-bitADR[2:0] of the image address ADR, exceeds “8” or not. If the value doesnot exceed “8”, only one page area is accessed horizontally, thus onlyone bank is subjected to an active operation. If the value exceeds “8”,a plurality of page areas are accessed horizontally, thus two banks haveto be subjected to an active operation. Then, the decoder DEC0 outputsselection control signals 0 through 7 of the selector SEL0 on the basisof the output of the comparator CMP3 that indicates that one bank or twobanks are active, as well as ADR[9]=POSY[3] and ADR[3]=POSX[3], which isthe fourth bit of the position information of the front pixel in theaccess area.

In the memory map shown in FIG. 159, each page area is constituted by8×8 pixels, thus the relationship between ADR[9]=POSY[3] andADR[3]=POSX[3], which are the fourth bit of the position informationPOSX, POSY of the front pixel, and the bank address BA[1:0] is asfollows.

ADR[9]=POSY[3], ADR[3]=POSX[3]=0, 0 BA[1:0]=0, 0 (bank BA0)ADR[9]=POSY[3], ADR[3]=POSX[3]=0, 1 BA[1:0]=0, 1 (bank BA1)ADR[9]=POSY[3], ADR[3]=POSX[3]=1, 0 BA[1:0]=1, 0 (bank BA2)ADR[9]=POSY[3], ADR[3]=POSX[3]=1, 1 BA[1:0]=1, 1 (bank BA3)Also, in a memory map that is different from the one shown in FIG. 159,the relationship with the above bank addresses differs.

FIG. 163 shows output signals of the decoder DEC0 (selection controlsignals 0 through 7 of the SEL0) corresponding to a combination of anoutput SIZE+ADR[2:0] of the adder ADD and ADR[9]=POSY[3],ADR[3]=POSX[3]. Furthermore, FIG. 163 shows input terminals ACTBA 0through 7 of the selector SEL0 that are selected in accordance with theoutput signals of the decoder DEC0 (selection control signals 0 through7 of the SEL0).

Specifically, the decoder DEC0 outputs the outputs “0” through “7” withrespect to the four combinations of ADR[9]=POSY[3], ADR[3]=POSX[3] forthe case in which SIZE+ADR[2:0] exceeds or does not exceed 8. Asdescribed above, the four combinations of ADR[9]=POSY[3], ADR[3]=POSX[3]are associated with bank addresses in which the front pixels of anaccess area are positioned. Also, in the case in which SIZE+ADR[2:0]does not exceed 8, only one bank may be active, and in the case in which[SIZE+ADR[2:0]] exceeds 8, two banks have to be activated.

The active bank number generating section 1612 shown in FIG. 161 has theselector SEL0 that selects values set to ACTBA 0 through 7 of a register543 in response to selections signals constituted by the outputs 0through 7 of the decoder DEC0, and the decoder DEC1 that converts theset values of ACTBA 0 through 7 of the register 543, which are selectedby the selector SEL0, to an active bank number ACT_BA[1:0], withreference to the Table.

FIG. 164 is a table for explaining the meanings of values 000b through111b that can be set to ACTBL of the register 543. It should be notedthat “b” means a binary notation. The set values 000b through 011bcorrespond to the case in which an active bank, which is subjected to anactive operation in accordance with an access area, is any of BA 0through 3, and set values 100b, 101b, 110b, and 111b each corresponds tothe case in which the active bank is BA0&1, BA0&2, BA2&3, or BA1&3. Abank, which is a target of background refresh operation, is as shown inFIG. 164, with respect to the bank activated in the normal memoryoperation, in accordance with the memory maps Maps 1, 2 and inaccordance with whether the background refresh is executed in two banksor one bank. Specifically, the background refresh operation target bankis as follows.

In the case of an active bankBA0 (setvalue 000b), refresh banks areBA2&3 (MAP1) or BA1&3 (Map2) in two-bank refresh, and the refresh bankis BA2 (Map1) or BA1 (Map2) in one-bank refresh.

In the case of an active bankBA1 (set value 001b), the refresh banks areBA2&3 (MAPL) or BA0&2 (Map2) in two-bank refresh, and the refresh bankis BA3 (Map1) or BA0 (Map2) in one-bank refresh.

In the case of an active bankBA2 (set value 010b), the refresh banks areBA0&1 (MAPL) or BA1&3 (Map2) in two-bank refresh, and the refresh bankis BA0 (Map1) or BA3 (Map2) in one-bank refresh.

In the case of an activebankBA3 (set value 011b), the refresh banks areBA0&1 (MAPL) or BA0&2 (Map2) in two-bank refresh, and the refresh bankis BA1 (Map1) or BA2 (Map2) in one-bank refresh.

In the case of active banks BA0&1 (set value 100b), the refresh banksare BA2&3 (MAP1) in two-bank refresh, and the refresh bank is BA2 or 3(Map1) in one-bank refresh. The memory map Map 2 is not applicable.

In the case of active banks BA0&2 (set value 101b), the refresh banksare BA1&3 (MAP2) in two-bank refresh, and the refresh bank is BA1 or 3(Map2) in one-bank refresh. The memory map Map 1 is not applicable.

In the case of active banks BA2&3 (set value 110b), the refresh banksare BA0-&1 (MAPL) in two-bank refresh, and the refresh bank is BA0 or 1(Map1) in one-bank refresh. The memory map Map 2 is not applicable.

In the case of active banks BA1&3 (set value 111b), the refresh banksare BA0&2 (MAP2) in two-bank refresh, and the refresh bank is BA0 or 2(Map2) in one-bank refresh. The memory map Map 1 is not applicable.

By defining the set values into the register 543 as described above, itis possible to arbitrarily set a memory mapping to be adopted in thesystem, the active bank number ACT_BA[1:0] corresponding to the eightcases of the outputs 0 through 7 of the decoder DEC0 in accordance withwhether a refresh is a two-bank refresh or one-bank refresh, and thebackground refresh bank number BR_BA[1:0], BR_A[3:0].

FIG. 165 is a figure showing a conversion table of the decoder DEC1.Active banks are associated with the outputs of the selectors SEL0(inputs of the DEC1), 0 through 7. This relationship is shown in FIG.164 as well. Here, the operation of the decoder DEC1 corresponding tothe examples of the register set values is described.

FIG. 166 is a table showing a conversion operation performed by thedecoder DEC1 corresponding to a first example of the register setvalues. The register set values of the first example correspond to thememory map Map1, and “01234466” are set in eight input terminals of theselector SEL0. Along with this, the decoder DEC1 generates outputs shownin FIG. 166 (DEC1 Output) with reference to the table of FIG. 165, inresponse to the output values “01234466” of the selector SEL0, which areselected in accordance with the selection signals of the selector SEL0(output signals of the decoder DEC0). When the selector output valuesare “0123”, one bank is selected, and when the selector output valuesare “4466”, two banks are selected.

FIG. 167 is a table showing a conversion operation of the decoder DEC1corresponding to a second example of the register set values. Theregister set values of the second example correspond to the memory mapMap2, and “01235577” are set in the eight input terminals of theselector SEL0. Along with this, the decoder DEC1 generates outputs shownin FIG. 167 (DEC1 Output) with reference to the table of FIG. 165, inresponse to the output values “01235577” of the selector SEL0. In thiscase as well, when the selector output values are “0213”, one bank isselected, and when the selector output values are “6677”, two banks areselected.

The background refresh bank number generating section 1613 shown in FIG.161 has a selector SEL1 that selects the set values set in BRBA 0through 3 of the register 543 by means of lower two bits of the outputof the selector SEL0, and a decoder DEC2 that converts the selectoroutput to a background refresh target bank numbers BR_BA[1:0],BR_A[3:0]. The background refresh target bank number BR_BA[1:0]corresponds to the case inwhich two-bank refresh is performed, andcorresponds to, for example, the bank address BA[1:0] shown in FIG. 117.Moreover, the background refresh target bank number BR_A[3:0]corresponds to the case in which one-bank refresh is performed, andcorresponds to, for example, the address terminal A[3:0] shown in FIG.118.

FIG. 168 is a table showing an operation of the selector SEL1. Thevalues of the BRBA 0 through 3 that are set in the register 543 areselected by using the lower two bits of the selector SEL0 as theselection signal.

FIG. 169 is a table showing a conversion table of the decoder DEC2.Decoder inputs (DEC2, Input) are values 0 through 7 that can be set inthe register 543 in accordance with BRBA 0 through 3, wherein values “0,1, 2, 3” correspond to one-bank refresh to refresh banks 0 through 3.Further, values “4” and “6” correspond to two-bank refresh when Map1 isused, and banks 0&1, 2&3 are refreshed. Also, values “5” and “7”correspond to two-bank refresh when Map2 is used, and banks 0&2, 1&3 arerefreshed. In this case as well, any values can be set in the register543 in accordance with the memory maps Map1 or Map2, and in accordancewith whether a refresh is the one-bank refresh or two-bank refresh.

FIG. 170 is a figure showing an operation of the decoder DEC2 in thecase of the first register set value. This example is applied to thetwo-bank refresh in the memory map Map1, and BRBA 0 through 3 are “6644”respectively in the case of the first register set value. The selectorSEL1 selects these set values in accordance with the lower two bits ofthe output of the selector SEL0, and the decoder DEC2 outputs thebackground refresh bank number BA[1:0] with reference to the conversiontable (FIG. 169). Specifically, if the input of the decoder DEC2 is “6”,banks Bank2&3 are refreshed, and if the input is “4”, banks Bank0&1 arerefreshed.

FIG. 171 is a figure showing an operation of the decoder DEC2 in thecase of the second register set value. This example is applied to thetwo-bank refresh in the memory map Map2, and BRBA 0 through 3 are “7755”respectively in the case of the second register set value. The selectorSEL1 selects these set values in accordance with the lower two bits ofthe output of the selector SEL0, and the decoder DEC2 outputs thebackground refresh bank number BA[1:0] with reference to the conversiontable (FIG. 169). Specifically, if the input of the decoder DEC2 is “7”,banks Bank1&3 are refreshed, and if the input is “5”, banks Bank0&2 arerefreshed.

FIG. 172 is a figure showing an operation of the decoder DEC2 in thecase of the third register set value. This example is applied to theone-bank refresh in the memory map Map1, and BRBA 0 through 3 are “2301”respectively in the case of the third register set value. The selectorSEL1 selects these set values in accordance with the lower two bits ofthe output of the selector SEL0, and the decoder DEC2 outputs thebackground refresh bank number A[3:0] with reference to the conversiontable (FIG. 169). Specifically, Banks 2, 3, 0, 1 are refreshed inaccordance with the inputs of the decoder DEC2, “2, 3, 0, 1”,respectively.

FIG. 173 is a figure showing an operation of the decoder DEC2 in thecase of the fourth register set-value. This example is applied to theone-bank refresh in the memory map Map2, and BRBA 0 through 3 are “1302”respectively in the case of the fourth register set value. The selectorSEL1 selects these set values in accordance with the lower two bits ofthe output of the selector SEL0, and the decoder DEC2 outputs thebackground refresh bank number A[3:0] with reference to the conversiontable (FIG. 169). Specifically, Banks 1, 0, 3, 2 are refreshed inaccordance with the inputs of the decoder DEC2, “1, 3, 0, 2”,respectively.

As described above, there are only four types of combinations of therefresh target banks with respect to the active banks in a normal accessoperation. Therefore, the inputs of the selector SEL1 are limited tofour, but any of the four inputs of the selector SEL1 is selected inaccordance with the lower two bits of the three-bit output value of theselector SEL0, whereby the refresh banks corresponding to the activebanks can be generated.

Returning to FIG. 161, a background refresh mode signal BRMD is inputtedto the controller 1615. This mode signal BRMD is a signal indicatingwhether a refresh is a four-bank refresh or two- or one-bank refresh,and is set into the register 543. In the casein which the mode signalBRMD is the four-bank refresh, the background refresh operation isprohibited.

The controller 1615 supplies selection signals S2, S3, S4 correspondingto commands BREN, ACT to selectors SEL 2, 3, 4 respectively, whenoutputting the commands to a command CMD in response to the backgroundrefresh enable signal BR_EN. In the case in which the background refreshenable signal BR_EN is in the H level, the controller 1615 causes theselector SEL2 to selects refresh burst length RBL A[7:4], causes theselector SEL3 to select a background refresh bank number BR_BA[1:0], andcauses the selector SEL4 to select a background refresh addressBR_A[3:0], when outputting the command BREN. As a result, the refreshburst length RBL is outputted from the address terminal A[7:4], and thebackground refresh bank number BR_BA[1:0] is outputted from the bankaddress terminal BA[1:0]. The controller 1615 then causes the selectorSEL2 to select other A[7:4], causes the selector SEL3 to select anactive bank number ACT_BA[1:0], and causes the selector SEL4 to selectother A[3:0], when outputting the command ACT. As a result, a normaladdress A[7:4] is outputted from the address terminal A[7:4], and anactive target selection bank address BA[1:0] is outputted from the bankaddress terminal BA[1:0].

FIG. 162 is a timing chart of the operation of the memory controller. Inthis example, the image processing device 81 outputs an image addressADR=0x000, size signal SIZE=32, access type signal ATYP=000b, andread/write signal RWX=H, while asserting the access request signal REQfrom a clock number 3, and further inputs 32 bytes of read data DATA in32-clock cycles, while asserting the strobe signal STB from a clocknumber 22.

On the other hand, the memory controller 82 determines, based on theimage address ADR=0x000, size signal SIZE=32, and access type signalATYP=000b, that a horizontal access is made to the position of a frontpixel of image data, POSX, POSY=0, 0, active bank ACT_BA=BA0, BA1, rowaddress RA0, A1, and column address CA0, and that a background refreshis performed on banks BR_BA=BA2, BA3 when the refresh burst lengthRBL=4. The memory controller 82 then outputs a background refreshcommand BREN, refresh banks BA 2, 3, and refresh burst length RBL=4 at aclock number 6, further outputs an active command ACT, bank address BA0,and row address RA0 at a clock number 8, outputs an active command ACT,bank address BA1, and row address RA1 at a clock number 10, subsequentlyoutputs a read command RD, bank address BA0, and column address CA0,then outputs a read command RD, bank address BA1, and column addressCA0, and outputs a pre-charge command PER, bank address BA0, pre-chargecommand PER, and bank address BA1. The burst length BL of each readcommand is 8. Therefore, the memory controller further outputs two pairsof the above-mentioned commands ACT, RD, PRE. As a result, 32 bytes ofdata d0 through d31 are received from the data terminals DQ of thememory device. Then, the memory controller outputs the data d0 throughd31 to the image processing device from the clock number 22 in 32-clockcycles.

The memory controller 82 outputs the appropriate refresh block count RBCto the memory along with the register set command EMRS, and sets therefresh block count RBC and the register set command EMRS into theregister of the memory. In this case, the memory controller 82determines the refresh burst length RBL from the number of clock cyclesrequired in data transfer, in view of the refresh block count RBC, thedata being obtained from the size signal SIZE. Moreover, the memorycontroller 82 outputs the refresh burst length RBL to the memory alongwith the register set command EMRS, and sets the refresh burst lengthRBL and the register set command EMRS into the register within thememory.

<<Method of Inputting Parameters>>

The above has described the function for various accesses and refreshesperformed on the memory device that stores two-dimensionally arrayeddata such as image data. In this case, parameters that are required forrealizing various functions are inputted from the memory controller tothe memory device. The method of inputting these parameters is describedhereinafter.

FIG. 174 is a figure showing a start byte signal SB in a byte boundary.As already described above, in the byte boundary, a start byte signal SBindicating the front byte within four bytes of memory unit area isinputted to the memory device. In FIG. 174, in the case in which anaccess target is an area 1740 straddling two adjacent page areas thatare selected by banks 0, 1 and a row address RA5, a start byte signalSB=2 is supplied to the memory device. Accordingly, two bytes of data B2and B3 out of the four bytes of data B0 through B3 selected by thecolumn address CA7, which are within a page area with bank 0 and rowaddress RA5, and two bytes of data B0, B1 out of the four bytes of dataB0 through B3 selected by the column address CA4, which are within apage area with bank 0 and row address RA5 are associated with theinput/output terminals, and the four bytes of data areinputted/outputted. The association of the four bytes of datacorresponds to the case in which the memory map 12 is in an up mode. Ina down mode, the association of the four bytes of data differs.

Moreover, in the memory device, since the column address CA4 of theadjacent page area is calculated from the column address CA7 of theaccess area 1740, the step number data CST of the column address withinthe page area is set to 4 in the register in advance.

FIG. 175 is a figure showing a relationship between second informationBMR and first information SB (start byte) of the byte combination data.In the upper half of FIG. 175, the second information BMR corresponds tothe up mode, and in the lower half the second information BMRcorresponds to the down mode. Each of these parts shows a 4-bytecombination that is associated with the input/output terminals inaccordance with the start byte SB=0 through 3. The up mode is as shownin FIG. 174. In the down mode, the arrangement of four bytes within a4-byte area is opposite to that of the up mode. Along with this, therelationship between the start byte SB and the 4-byte combinationassociated with the input/output terminals is opposite to that of the upmode. The second information BMR is also inputted to the memory device,and is set according to need.

FIG. 176 is a figure showing the row address step RS. In a multi-bankaccess, on the basis of the bank address and row address of the upperleft page area of a rectangular access page area 1760, the memory deviceobtains the remaining bank addresses and row addresses. In order to doso, step information RS of the row addresses is required as theinformation on the memory map 12. Therefore, the memory device inputsthe row address step information RS and sets the row address stepinformation RS into the register according to need. In the case of therectangular access area 1760, the bank address BA3 and row address RA1are provided along with an active command, and, in the case of four-bankaccess (multi-bank information SA′=4), row addresses RA2, RA5, RA6 areobtained based on RS=4.

FIG. 177 is a figure showing the memory mapping information AR. Thefigure shows two types of memory mapping. For example, in the case ofType A, AR=0 is inputted, and in the case of Type B, AR=1 is inputtedinto the memory device, and both are set into the register. Inmulti-bank access, the access target banks are calculated based on thememory mapping information AR. Moreover, even in a background refresh,the refresh target banks are obtained based on the memory mappinginformation AR. In the Type A, the odd-numbered rows are constituted bybanks 0, 1, while the even-numbered rows are constituted by banks 2, 3.In the Type B, the odd-numbered rows are constituted by banks 0, 2,while the even-numbered rows are constituted by banks 1, 3. The rowaddresses RA are the same. The example of FIG. 176 shows the Type A.

FIG. 178 is a figure showing the refresh burst length RBL and therefresh block count RBC in a background refresh. In the backgroundrefresh, a refresh operation is repeated a number of times correspondingto the refresh burst length RBL in response to a command, and eachrefresh operation is performed in parallel in the blocks of the refreshblock count RBC. FIG. 178(A) is an example in which RBC=2 and RBL=6,wherein a refresh is performed six times by means of a total of twelveword lines. FIG. 178(B) is an example in which RBC=3 and RBL=4, and inthis case as well, a refresh is performed four times by means of a totalof twelve word lines. FIG. 178(C) is an example in which RBC=4 andRBL=3, and in this case well, a refresh is performed three times bymeans of a total of twelve word lines.

As described above, the memory device needs to input required parametersin order to realize various accesses. As the method of inputting theseparameters, there is a method of using a special input terminal, and amethod of using an unused address input terminal. Furthermore, themethod of inputting the parameters varies according to whether thememory device is constituted by a single data rate or double data rateSDRAM. The method of inputting the parameters also varies according towhether the address is subjected to multiple input (multiplex system) ornon-multiple input (non-multiplex system) These matters are descriedhereinafter.

FIG. 179 is a figure showing a configuration of the special inputterminal of the memory device, an input buffer thereof, and a moderegister. A parameter signal that is inputted by the special inputterminal SP is inputted to a special input buffer 1790, a latched signal1792 is then set into a mode register 1791, and the set signal 1793 issupplied to an unshown internal circuit. However, in the case in whichthe function corresponding to the parameter signal (byte boundaryfunction, multi-bank access function, background refresh function) isdisabled, the corresponding parameter needs to be set to a defaultvalue.

Here, in accordance with an enable signal 1794, which indicates whetherthe functions are enabled disabled, if the functions are enabled, theinputted parameters are set in the mode register 1791, and if thefunctions are disabled, the default values are set into the moderegister 1791 as the parameters. Moreover, the input buffer 1790introduces signals from the special input terminal SP if the functionsare enabled, but the enable signal 1794 is clamped to the H level if thefunctions are disabled. Therefore, in the case of the disabledfunctions, it is not necessary to connect the special input terminal SPand the input buffer 1790 by means of a bonding wire.

FIG. 180 is a figure showing a configuration of the special inputterminal, input buffer thereof, and mode register within the memorydevice. Here, there is shown an example in which, out of the variousparameters, the start byte SB, multi-bank information SA′, and refreshbank information SA are inputted from the special input terminal.

A two-bit start byte SB is inputted from a special input terminal SP0,then introduced to an input buffer 1790-0, and set into a mode register1791-0. Setting into the mode register 1791-0 is performed in responseto a mode register set pulse MRSPZ. However, in the case in which anenabled signal 1800 is disabled, the mode register 1791-0 is set to adefault value (SB=0, start byte=0), and the output of the input buffer1790-0 is clamped. This enable signal 1800 is supplied from a moderegister MRS, bonding option, fuse circuit and the like, which are notshown.

Similarly, two-bit multi-bank information SA′ then inputted from aspecial input terminal SP1, and introduced into an input buffer 1790-1,and is set into a mode register 1791-1. Setting into the mode register1791-1 is performed in response to the mode register set pulse MRSPZ. Inthe case in which the enable signal 1800 is disabled, the value of themode register is set to a default value in the same manner describedabove (SA′=0, only one bank is selected), and the output of the inputbuffer is clamped.

Similarly, two-bit refresh bank information SA is inputted from aspecial input terminal SP2, and set into a mode register 179102.Further, in the case in which an enable signal 1802 is disabled, thevalue of the mode register is set to a default value in the same mannerdescribed above (SA=3, all banks are selected), and the output of theinput buffer is clamped. The two-bit information items SB, SA′ areinputted from two special terminals in parallel, respectively.Alternatively, these information items may be inputted serially from onespecial terminal.

FIG. 181 is a figure showing an example of the mode register. In thisexample, the abovementioned parameters are set inputted from addressterminals and set into the mode register. The figure shows mode registerareas 1810, 1811 and 1812. Input values and set values of addressterminals A0 through A6 are shown in accordance with each combination ofbank addresses BA0, BA1, and a rising edge RiseEdge and a falling edgeFallEdge of a synchronous clock.

First, when a mode register set command MRS is inputted along with thebank addresses BA0=0, BA1=0, burst lengths that are inputted from theaddress terminals A0 through A2 and read latencies that are inputtedfrom the address terminals A3 through A5 are set into the mode register1810 at the clock rising edge RiseEdge, while write recovery values thatare inputted from the address terminals A0 through A2 are set at thefalling edge FallEdge.

Next, when the mode register set command MRS is inputted along with thebank addresses BA0=1, BA1=0, values (not shown) that are inputted fromthe address terminals A0 through A5 are set into the mode register 1811at the clock rising edge RiseEdge, and a byte shift function flag BS,second information BMR of the byte combination information, multi-bankfunction flag MB, a background refresh function flag BR, and memorymapping information AR that are inputted from the address terminals A0through A4 are set at the falling edge FallEdge. It should be noted thatthere are shown only the information items that indicate whether thesignals are enabled or disabled. However, as described above,information that indicates the byte shift information SB, multi-bankinformation SA′, refresh bank information SA, refresh block count RBC orthe like can also be set.

Furthermore, when the mode register set command MRS is inputted alongwith the bank addresses BA1=0, BA1=1, the row address step informationRS that is inputted from the address terminals A0 through A5 is set intothe mode register 1812 at the clock rising edge RiseEdge, and the rowaddress step information RS that is inputted from the address terminalsA0 through A5 is set at the falling edge FallEdge.

It should be noted that the mode register areas are used when testsetting is performed when the bank addresses are BA0=1, BA1=1. A table1813 shows a normal mode register MRS and an extended mode register EMRSthat correspond to the combinations of the bank addresses BA0, BA1.Moreover, tables 1814 through 1819 each shows the values of the addressterminals A0 through A6 in the mode register area 1811, and the setvalues thereof.

FIG. 182 is a figure showing an example of an enable signal generatingcircuit. FIG. 182(A) shows enable signal generating circuits 1820, 1821that are set by bonding options. The enable signal generating circuit1820 has a bonding operation terminal 1825, a power source terminal Vdd,and a ground terminal Vss. The bonding operation terminal 1825 isconnected to the power source terminal Vdd by means of a bonding wire,whereby the enable signal 1794 becomes Vdd, and a special accessfunctions is enabled. On the other hand, the enable signal generatingcircuit 1821 connects the bonding operation terminal 1825 and the groundterminal Vss by means of a bonding wire, whereby the enable signal 1794becomes Vss, and disables the access function.

FIG. 182(B) shows enable signal generating circuits 1822, 1823 that areset by fuse FS. The enable signal generating circuit 1822 is constitutedby a power source Vdd, ground power source Vss, resistance R1, and fuseFS. By fusing the fuse FS, the enable signal 1794 becomes Vdd and entersan enabled state. The enable signal generating circuit 1823 does notfuse the fuse, thus the enable signal 1794 becomes Vss and enters adisabled state.

FIG. 183 is a figure showing an input method in a single data rate(SDR). The figure shows an example in which the parameters are inputtedfrom special terminals (Special Pin 0, 1). In (A) of the figure, alongwith a background refresh command BREN, the bank addresses BA0, BA1 areinputted from the bank address terminals, and the refresh bankinformation SA0, SA1 are inputted from the special terminals, insynchronization with a rising edge of a clock CLK (solid line). In (B)of the figure, along with an active command ACT, the bank addresses BA0,BA1 are inputted from the bank address terminals, and the multi-bankinformation SA′0, SA′1 are inputted from the special terminals, insynchronization with the rising edge of the clock CLK. Although notshown, parameters such as RBL, RBC, AR, RST, CS and the like areinputted from the special terminals along with an extended mode registerset command EMRS, in synchronization with the rising edge of the clockCLK.

FIG. 184 is a figure showing an input method in a double data rate(DDR). In this example as well, the parameters are inputted from thespecial terminals (Special Pin). The relationship between each commandand each parameter is the same as the one shown in FIG. 183. Sincedouble data rate is shown in FIG. 184, the bank addresses BA0, 1, andthe parameters SAO, SA1, SA′0, SA′1, SB0, and SB1 are inputted insynchronization with the rising edge and falling edge of the clock.

Next, there is described a method of inputting the parameters fromunused address terminals without using the special terminals.

FIG. 185 is a figure showing an input method using an ADQ multiplexinput system. In the ADQ multiplex input system, an address inputterminal and a data input/output terminal are configured by a commonterminal, wherein a command is inputted along with an address, andthereafter data is inputted/outputted. Then, in the case in which thenumber of address terminals is higher than the number of data terminals,the parameters can be inputted from the common terminal along with theaddresses, when inputting/outputting the command.

FIG. 185(A) shows a configuration of the input circuit, which isprovided with common terminals ADQ (A/DQ0 through A/DQ20, 21 bits) anddata terminals DQ (DQ21 through DQ31, 11 bits). The addresses and datashare the common terminals ADQ, and only the data use the data terminalsDQ. These data terminals DQ can be used to input the parameters. Thecommon terminal ADQ is connected to an address buffer 1850 and aninput/output buffer 1852-0, and the address buffer 1850 and theinput/output buffer 1852-0 are connected to an address latch circuit1851 and a memory cell 1853-0 respectively. Also, the data terminal DQis connected to a special buffer 1854 and an input/output buffer 1852-1,and the special buffer 1854 and the input/output buffer 1852-1 areconnected to a mode selector 1855 and a memory cell 1853-1 respectively.

FIG. 185(B) shows a timing chart, and is an example of SDR. First, a21-bit address ADD is inputted along with a write command WR from thecommon terminal ADQ, and a parameter SP is inputted from the dataterminal DQ. The address ADD is introduced into the address buffer 1850,and the parameter SP is introduced into the special buffer 1854. 32-bitdata is inputted from the common terminal ADQ and the data terminal DQafter a lapse of three clocks since the command WR has been inputted. Ifthe command is a read command, data is outputted. The parameter SP thatis inputted along with the command is, for example, the multi-bankinformation SA′, refresh bank information SA, start byte SB, or thelike.

In the ADQ multiplex, row and column addresses are inputted at oncealong with the command, and thereafter the data is inputted/outputted,without inputting the active command and the write command in atime-division manner as in an SDRAM. Therefore, when the command and theaddress are inputted, the parameters can be inputted from unused dataterminals DQ.

FIG. 186 is a figure showing an in input method using an addressmultiplex input system. As the address multiplex input system, there isan input system for an SDRAM or the like. An address terminal Add isshared by a row address and a column address, and the row address andthe column address are inputted from the common address terminal Add ata RAS cycle and a CAS cycle respectively. However, in the case in whichthe number of row addresses is higher than the number of columnaddresses due to the configuration of the memory cell array, theparameters can be inputted from an address terminal that is not used atthe time of the CAS cycle. For example, the start byte SB can beinputted at the CAS cycle.

FIG. 186(A) shows a configuration of an input circuit, wherein theaddress terminals Add (Add 0 no through 7, 8 bits) are connected to anaddress buffers 1850-0, 1850-1, and the address buffers are connected toa row address latch circuit 1851-0 and a column address latch circuit1851-1 respectively. Also, address terminals Add (Add 8 through 13, 6bits) are connected to an address buffer 1850-2 and a start byte buffer1860, and the address buffer 1850-2 and start byte buffer 1860 areconnected to a row address latch circuit 1851-2 and a start byteselector circuit 1861 respectively.

FIG. 186(B) shows a timing chart, and is an example of SDR. First, anactive command AC and 14 bits of row address RA are inputted at a RAScycle from the address terminals Add[7:0], Add[13:8], and 8 bits ofcolumn address CA and a start byte SB[1:0] are inputted at a CAS cyclefrom the address terminals Add[7:0] and any of the address terminalsAdd[13:8] respectively, along with a read or write command RD/WR.

FIG. 187 is a figure showing the input method using the addressmultiplex system in the double data rate (DDR). At the RAS cycle inwhich the active command ACT is inputted, the 14-bit row address RA isinputted from the address terminals Add[7:0] and Add[13:8] insynchronization with the clock rising edge, and the parameter SP isinputted from the address terminals add[7:0] and Add[13:8] insynchronization with the clock falling edge. This parameter SP is, forexample, the row address step information RS, memory map information AR,multi-bank information SA′, or the like.

Also, at the CAS cycle in which the read or write command RD/WR isinputted, the 8-bit column address CA is inputted from the addressterminals Add[7:0] in synchronization with the clock rising edge, andthe parameter SP is inputted from any of the address terminals Add[7:0]in synchronization with the clock falling edge. This parameter SP is,for example, the start byte SB, column address step information CST,access rectangle size information (W, H), bite combination secondinformation BMR (UP, DOWN, ALL, EVEN, ODD), or the like.

In the case of DDR and address multiplex system, there are a total offour input timings, thus unused address terminals can be used to inputthe parameters.

FIG. 188 is a figure showing the input method using the addressmultiplex system in the double data rate (DDR). In this example, thenumber of address terminals is reduced to eight bits of Add[5:0] andAdd[7:6]. In the case of DDR and address multiplex system, there are atotal of four input timings, thus the unused address terminals stillexist even if the number of address terminals is reduced as describedabove. Therefore, the parameters can be inputted from the unused addressterminals.

First of all, at the RAS cycle in which an active command ACT isinputted, an 8-bit row address RA is inputted from the address terminalsAdd[5:0] and Add[7:6] in synchronization with the clock rising edge, a6-bit row address RA is inputted from the address terminals Add[5:0] insynchronization with the clock falling edge, and the parameter SP isinputted from the address terminals Add[7:6]. This parameter SP is, forexample, the multi-bank information SA′, row address step informationRS, memory map information AR, or the like.

Also, at the CAS cycle in which a read or write command RD/WR isinputted, an 8-bit column address CA is inputted from the addressterminals Add[5:0] and Add[7:6] in synchronization with the clock risingedge, and the parameter SP is inputted from any of the address terminalsAdd[5:0], Add[7:6] in synchronization with the clock falling edge. Thisparameter SP is, for example, the start byte SB, column address stepinformation CST, access rectangle size information (W, H), bitscombination second information BMR (UP, DOWN, ALL, EVEN, ODD), or thelike.

As described above, the parameters that are required for realizing thespecial functions for byte boundary access, multi-bank access andbackground refresh can be inputted from the special terminals or unusedaddress terminals. The method of inputting the optimum parameters isselected, the method corresponding to the input system of the memorydevice.

According to the present invention, the memory cores are caused toexecute the refresh operation a number of times corresponding to aplurality of refresh counts, which is set in the refresh target bank,thus the normal memory operation can be started on the refresh targetbank within a short time after the background refresh operation isended, and the decrease of the effective bandwidth can be prevented.

According to the present invention, during the normal memory operationexecuted by the other memory bank, the memory cores are caused toexecute the refresh operation a number of times corresponding to aplurality of refresh counts, which is set in the set refresh targetbank, thus the refresh operation and the normal memory operation can beexecuted in parallel, and the decrease of the effective bandwidth in thenormal memory operation, which is caused by the refresh operation, canbe prevented. Moreover, the number of times of the background refreshoperation performed during the normal memory operation is setbeforehand, thus the normal memory operation can be started in therefresh target bank within a short time after the background refreshoperation is ended, and the decrease of the effective bandwidth can beprevented.

Further, since the memory device repeats an ordinary memory operation ata specific bank during the horizontal access period, the memory deviceperforms the ordinary memory operation at the selected bank, andperforms the refresh operation at a refresh target bank other than thehorizontal access target bank. On the other hand, since it can not bepredictable which bank will be a memory access target bank during therectangular access period, it is prohibited to perform the refreshoperation together with the ordinary memory operation. The horizontalaccess can be continued during the back ground refresh operation,accordingly, so that the effective bandwidth can be larger.

1. A memory device, comprising: a plurality of banks which respectivelyhave memory cores including memory cell arrays and are selected by bankaddresses; and a control circuit, which, in response to a backgroundrefresh command and refresh burst length information, causes the memorycores within refresh target banks to successively execute refreshoperation a number of times corresponding to the refresh burst lengthinformation.
 2. A memory device which is operated in response to acommand from a memory controller, the memory device comprising: aplurality of banks which respectively have memory cores including memorycell arrays and are selected by bank addresses; and a control circuit,which, in response to a background refresh command, causes the memorycores within refresh target banks set by the memory controller tosuccessively execute refresh operation a number of times correspondingto refresh burst length that is set by the memory controller, and, whilethe memory cores within the refresh target banks is executing therefresh operation, in response to a normal operation command, furthercauses the memory cores within banks other than the refresh target banksand selected by the bank addresses to execute normal memory operationcorresponding to the normal operation command.
 3. The memory deviceaccording to claim 2, further comprising a refresh address counter whichcounts refresh target addresses within each of the plurality of banks orwithin each of a plurality of groups of the plurality of banks, whereinthe control circuit has: a background refresh controller which outputsrefresh control signals to the set refresh target banks in response tothe background refresh command; a refresh burst length register in whichthe refresh burst length is set; and a core controller which is providedin each of the plurality of banks, and, in response to the backgroundrefresh control signals, causes the memory cores to execute refreshoperation on the addresses of the refresh address counter a number oftimes corresponding to the refresh burst length set in the refresh burstlength register.
 4. The memory device according to claim 2, wherein arefresh block count which indicates the number of memory blocksactivated simultaneously in a single refresh cycle is supplied, and thecontrol circuit causes the refresh target banks to execute the refreshoperation a number of times corresponding to the set refresh burstlength, in response to the background refresh command, the refreshoperation being performed for simultaneously activating the memoryblocks for the number of the refresh block count.
 5. The memory deviceaccording to claim 3, wherein the background refresh command and therefresh burst length are inputted simultaneously, the refresh burstlength register is provided in each of the banks, and the inputtedrefresh burst length is set into the refresh burst length registerwithin the refresh target bank.
 6. The memory device according to claim4, further comprising a refresh block count register, wherein thebackground refresh command and the refresh block count are inputtedsimultaneously, and the inputted refresh block count is set into therefresh block count register.
 7. The memory device according to claim 3,wherein the refresh burst length register is provided within a moderegister, a mode register set command and the refresh burst length areinputted simultaneously, and the inputted refresh burst length is setinto the refresh burst length register provided within the moderegister.
 8. The memory device according to claim 4, wherein the refreshblock count register is provided within a mode register, a mode registerset command and the refresh block count are inputted simultaneously, andthe inputted refresh block count is set into the refresh block countregister provided within the mode register.
 9. The memory deviceaccording to claim 3, wherein during the refresh operation executed anumber of times corresponding to the refresh burst length, the corecontroller causes, in response to a newly inputted background refreshcommand, the memory cores within the refresh target banks tosuccessively execute the refresh operation a number of times that isobtained by adding the refresh burst length to the remaining number oftimes of the refresh operation.
 10. The memory device according to claim3, wherein during the refresh operation executed a number of timescorresponding to the refresh burst length, the core controller causes,in response to a newly inputted background refresh command, the memorycores within the refresh target banks to successively execute therefresh operation a number of times corresponding to the refresh burstlength, regardless of the remaining number of times of the refreshoperation.
 11. The memory device according to claim 3, wherein the corecontroller causes, in response to a refresh-all command, the memorycores within the refresh target banks to repeatedly execute the refreshoperation from the address of the refresh address counter for theremaining addresses.
 12. The memory device according to claim 3, whereinduring the refresh operation performed a number of times correspondingto the refresh burst length, the core controller causes the memory coreswithin the refresh target banks to stop the refresh operation, inresponse to a background refresh stop command.
 13. The memory deviceaccording to claim 12, wherein, in response to the background refreshstop command, the core controller does not start a subsequent refreshoperation after causing the memory cores within the refresh target banksto end the refresh operation that is being executed.
 14. The memorydevice according to claim 3, wherein, on the basis of setting of anactive refresh interlock flag in the mode register, the backgroundrefresh controller supplies the background refresh control signals tobanks other than an access target bank corresponding to a bank addressto be inputted, in response to a normal memory operation command. 15.The memory device according to claim 3, wherein the core controller hasa refresh-burst length counter for count up in every refresh operation,and the core controller resets the refresh burst length counter inresponse to the background refresh command, and causes the memory coreswithin the refresh target banks to execute the refresh operation until acounter value of the refresh burst length counter reaches the refreshburst length that is set in the refresh burst length register.
 16. Thememory device according to claim 3, wherein the core controller has arefresh burst length counter for counted down in every refreshoperation, and the core controller sets the refresh burst length intothe refresh burst length counter in response to the background refreshcommand, and causes the memory cores within the refresh target banks toexecute the refresh operation until a counter value of the refresh burstlength counter reaches zero.
 17. A memory device which is operated inresponse to a command sent from a memory controller, the memory devicecomprising: a plurality of banks which respectively have memory coresincluding memory cell arrays and are selected by bank addresses; and acontrol circuit which controls operation of the memory cell arrayswithin the banks, wherein each of the plurality of banks storestwo-dimensionally arrayed data on the basis of a memory mapping of whicha memory logical space has a plurality of page areas that are selectedby the bank addresses and row addresses, in which the plurality of pageareas are arranged in rows and columns, and in which adjacent page areasare associated with different bank addresses, and during a period ofhorizontal access in which the two-dimensionally arrayed data isaccessed horizontally, the control circuit causes the memory coreswithin banks selected by the bank addresses to execute normal memoryoperation corresponding to a normal operation command in response to thenormal operation command corresponding to the horizontal access, andfurther causes a memory core within a refresh target bank other than thehorizontal access target bank to execute refresh operation in responseto a background refresh command.
 18. The memory device according toclaim 17, wherein, during a period of rectangular access in which anarbitrary rectangular area of the two-dimensionally arrayed data isaccessed, the control circuit causes the memory cores within the banksselected by the bank addresses and within banks adjacent to the selectedbanks, to execute the normal memory operation in response to the normaloperation command, and prohibits the refresh operation during the normalmemory operation.
 19. A memory system, comprising: a memory controller;and a memory device which is operated in response to a command from thememory controller, wherein the memory device has: a plurality of bankswhich respectively have memory cores including memory cell arrays andare selected by bank addresses; and a control circuit, which, inresponse to a background refresh command, causes the memory cores withinrefresh target banks set by the memory controller to successivelyexecute refresh operation a number of times corresponding to refreshburst length that is set by the memory controller, and, during therefresh operation executed by the memory cores within the refresh targetbanks, in response to a normal operation command, further causes thememory cores within banks other than the refresh target banks andselected by the bank addresses to execute normal memory operationcorresponding to the normal operation command.
 20. A memory controllerwhich controls a memory device having: a plurality of banks thatrespectively have memory cores including memory cell arrays and areselected by bank addresses; and a control circuit which controlsoperation of the memory cores within the plurality of banks, the memorycontroller comprising: a sequencer which, in response to an accessrequest from a host device, supplies a normal operation commandcorresponding to the access request and the bank addresses to the memorydevice, and causes the memory cores within normal access target banksselected by the bank addresses to execute normal operation, thesequencer, in response to the access request, supplying, to the memorydevice, refresh bank information specifying banks other than the normalaccess target banks, and refresh burst length designating the number oftimes that refresh operation is performed, along with a backgroundrefresh command, and, during the normal operation, causing the memorycores within refresh target banks related to the refresh bankinformation to successively execute the refresh operation a number oftimes corresponding to the refresh burst length.
 21. The memorycontroller according to claim 20, wherein the sequencer determineswhether the background refresh command can be issued or not, on thebasis of information indicating an access target data area in responseto the access request, and, if the background refresh command can beissued, obtains the refresh bank information and the refresh burstlength on the basis of the information indicating an access target dataarea.
 22. The memory controller according to claim 21, furthercomprising a register in which are set memory map information forassociating two-dimensionally arrayed data with a memory space, and banknumber information for executing the refresh operation corresponding tothe background refresh command, wherein the sequencer obtains therefresh bank information and the refresh burst length on the basis ofthe information indicating an access target data area and the setinformation of the register.
 23. A memory system, comprising: a memorycontroller; and a memory device which is operated in response to acommand from the memory controller, wherein the memory device has aplurality of banks which respectively have memory cores including memorycell arrays and are selected by bank addresses, each of the plurality ofbanks stores two-dimensionally arrayed data on the basis of a memorymapping of which a memory logical space has a plurality of page areasthat are selected by the bank addresses and row addresses, in which theplurality of page areas are arranged in rows and columns, and in whichadjacent page areas are associated with different bank addresses, andthe memory device further has a control circuit which causes the memorycores within banks selected by the bank addresses to execute normalmemory operation corresponding to a normal operation command in responseto the normal operation command during a period of horizontal access inwhich the two-dimensionally arrayed data is accessed horizontally, andfurther causes a memory core within a refresh target bank other than thehorizontal access target bank to execute refresh operation in responseto a background refresh command.
 24. The memory system according toclaim 23, wherein, during a period of rectangular access in which anarbitrary rectangular area of the two-dimensionally arrayed data isaccessed, the control circuit causes the memory cores within the banksselected by the bank addresses and within banks adjacent to the selectedbanks, to execute the normal memory operation in response to the normaloperation command, and prohibits the refresh operation during the normalmemory operation.
 25. A memory controller which controls a memory devicehaving: a plurality of banks which respectively have memory coresincluding memory cell arrays and are selected by bank addresses; and acontrol circuit which controls operation of the memory cores within theplurality of banks, wherein each of the plurality of banks storestwo-dimensionally arrayed data on the basis of a memory mapping of whosea memory logical space has a plurality of page areas that are selectedby the bank addresses and row addresses, in which the plurality of pageareas are arranged in rows and columns, and in which adjacent page areasare associated with different bank addresses, and the memory controllerhas a sequencer which, in response to an access request from a hostdevice, determines that the access request is for horizontal access inwhich the two-dimensionally arrayed data is accessed in a horizontaldirection, supplies a normal operation command corresponding to thehorizontal access and the bank addresses to the memory device, andcauses the memory cores within horizontal access target banks selectedby the bank addresses to execute normal operation, the sequencer, inresponse to the access request, supplying refresh bank information forspecifying banks other than the horizontal access target banks, and abackground refresh command to the memory device, and, during the normaloperation, causing the memory cores within refresh target banks relatedto the refresh bank information to execute the refresh operation. 26.The memory controller according to claim 25, wherein when the accessrequest is for rectangular access in which an arbitrary rectangular areaof the two-dimensionally arrayed data is accessed, the sequencersupplies a normal operation command corresponding to the rectangularaccess and the bank addresses to the memory device, and causes thememory cores within access target banks selected by the bank addressesto execute normal operation, but does not issue the background refreshcommand during the normal memory operation.